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| ispXPGA Family TM March 2003 Preliminary Data Sheet Non-volatile, Infinitely Reconfigurable * Instant-on - Powers up in microseconds via on-chip E2CMOS(R) based memory * No external configuration memory * Excellent design security, no bit stream to intercept * Reconfigure SRAM based logic in milliseconds Eight sysCLOCKTM Phase Locked Loops (PLLs) for Clock Management * * * * * True PLL technology 10MHz to 320MHz operation Clock multiplication and division Phase adjustment Shift clocks in 250ps steps High Logic Density for System-level Integration * * * * 139K to 1.25M system gates 160 to 496 I/O 1.8V, 2.5V, and 3.3V VCC operation Up to 414Kb sysMEMTM embedded memory sysIOTM for High System Performance High Performance Programmable Function Unit (PFU) * Four LUT-4 per PFU supports wide and narrow functions * Dual flip-flops per LUT-4 for extensive pipelining * Dedicated logic for adders, multipliers, multiplexers, and counters * High speed memory support through SSTL and HSTL * Advanced buses supported through PCI, GTL+, LVDS, BLVDS, and LVPECL * Standard logic supported through LVTTL, LVCMOS 3.3, 2.5, and 1.8 * Programmable drive strength for series termination * Programmable bus maintenance sysHSITM Capability for Ultra Fast Serial Communications * Up to 850Mbps performance * Up to 20 channels per device * Built in Clock Data Recovery (CDR) and Serialization and De-serialization (SERDES) Variable-Length Interconnect Routing Technology * Optimum speed, power, and flexibility for logic interconnections Flexible Memory Resources Flexible Programming, Reconfiguration, and Testing * IEEE 1532 and 1149.1 compliant * Microprocessor configuration interface * Program E2CMOS while operating from SRAM * Multiple sysMEM Embedded RAM Blocks - Single port, Dual port, and FIFO operation * 64-bit distributed memory in each PFU - Single port, Double port, FIFO, and Shift Register operation Table 1. ispXPGA Family Selection Guide ispXPGA 125 System Gates PFUs LUT-4s Logic FFs sysMEM Memory Distributed Memory EBR sysHSI Channels User I/O Packaging 139K 484 1936 3.8K 92K 30K 20 4 160/176 256 fpBGA 516 fpBGA1 ispXPGA 200 210K 676 2704 5.4K 111K 43K 24 8 160/208 256 fpBGA 516 fpBGA1 ispXPGA 500 476K 1764 7056 14.1K 184K 112K 40 12 336 516 fpBGA1 900 fpBGA 1. Thermally enhanced package. ispXPGA 1200 1.25M 3844 15376 30.7K 414K 246K 90 20 496 680 fpSBGA1 900 fpBGA Note: LFX1200B/C is preliminary, LFX125/200/500B/C information is advanced. (c) 2003 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 xpga_04 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Family Overview The ispXPGA family of devices allows the creation of high-performance logic designs that are both non-volatile and infinitely re-programmable. Other FPGA solutions force a compromise being either re-programmable or non-volatile. This family couples this capability with a mainstream architecture containing the features required for today's system-level design. Electrically Erasable CMOS (E2CMOS) memory cells provide the ispXPGA family with non-volatile capability. These allow logic to be functional microseconds after power is applied, allowing easy interfacing in many applications. This capability also means that expensive external configuration memories are not required and that designs can be secured from unauthorized read back. Internal SRAM cells allow the device to be infinitely reconfigured if desired. Both the SRAM and E2CMOS cells can be programmed and verified through the IEEE 1532 industry standard. Additionally, the SRAM cells can be configured and read-back through the sysCONFIGTM peripheral port. The family spans the density and I/O range required for the majority of today's logic designs, 139K to 1.25M system gates and 160 to 496 I/O. The devices are available for operation from 1.8V, 2.5V, and 3.3V power supplies, providing easy integration into the overall system. The system-level needs of designers are met through the incorporation of sysMEM dual-port memory blocks, sysIO advanced I/O support, and sysCLOCK Phase Locked Loops (PLLs). High-speed serial communications are supported through multiple sysHSI blocks, which provide clock data recovery (CDR) and serialization/de-serialization (SERDES). The ispLEVERTM design tool from Lattice allows designers easy implementation of designs using the ispXPGA product. Synthesis library support is available for the major logic synthesis tools. The ispLEVER tool takes the output from these common synthesis packages and place and routes the design in the ispXPGA product. The tool allows floor planning and the management of other constraints within the device. The tool also provides outputs to common timing analysis tools for timing analysis. To increase designer productivity, Lattice provides a variety of pre-designed modules referred to as IP cores for the ispXPGA product. These IP cores allow designers to concentrate on the unique portions of their design while using pre-designed block to implement standard functions such as bus-interfaces, standard communication-interfaces, and memory-controllers. Through the use of advanced technology and innovative architecture the ispXPGA FPGA devices provide designers with excellent speed performance. Although design dependent, many typical designs can run at over 150MHz. Certain designs can run at over 300MHz. Table 2 details the performance of several building blocks commonly used by logic designers. Table 2. ispXPGA Speed Performance for Typical Building Blocks Function 8:1 Asynch MUX 1:32 Asynch Demultiplexer 8 x 8 2-LL Piped Multiplier 32-bit Up/Down Counter 32-bit Shift Register Performance 150 MHz 125 MHz 225 MHz 290 MHz 360 MHz 2 Lattice Semiconductor ispXPGA Family Data Sheet Architecture Overview The ispXPGA architecture is a symmetrical architecture consisting of an array of Programmable Function Units (PFUs) enclosed by Input Output Groups (PICs) with columns of sysMEM Embedded Block RAMs (EBRs) distributed throughout the array. Figure 1 illustrates the ispXPGA architecture. Each PIC has two corresponding sysIO blocks, each of which includes one input and output buffer. On two sides of the device, between the PICs and the sysIO blocks, there are sysHSI High-Speed Interface blocks. The symmetrical architecture allows designers to easily implement their designs, since any logic function can be placed in any section of the device. The PFUs contain the basic building blocks to create logic, memory, arithmetic, and register functions. They are optimized for speed and flexibility allowing complex designs to be implemented quickly and efficiently. The PICs interface the PFUs and EBRs to the external pins of the device. They allow the signals to be registered quickly to minimize setup times for high-speed designs. They also allow connections directly to the different logic elements for fast access to combinatorial functions. The sysMEM EBRs are large, fast memory elements that can be configured as RAM, ROM, FIFO, and other storage types. They are designed to facilitate both single and dual-port memory for high-speed applications. These three components of the architecture are interconnected via a high-speed, flexible routing array. The routing array consists of Variable Length Interconnect (VLI) lines between the PICs, PFUs, and EBRs. There is additional routing available to the PFU for feedback and direct routing of signals to adjacent PFUs or PICs. The sysIO blocks consist of configurable input and output buffers connected directly to the PICs. These buffers can be configured to interface with 16 different I/O standards. This allows ispXPGA to interface with other devices without the need for external transceivers. The sysHSI blocks provide the necessary components to allow the ispXPGA device to transfer data at up to 850Mbps using the LVDS standard. These components include serializing, de-serializing, and clock data recovery (CDR) logic. The sysCLOCK blocks provide clock multiplication/division, clock distribution, delay compensation, and increased performance through the use of PLL circuitry that manipulates the global clocks. There is one sysCLOCK block for each global clock tree in the device. 3 Lattice Semiconductor Figure 1. ispXPGA Block Diagram ispXPGA Family Data Sheet PFU PIC sysMEM Block sysCLOCK PLL sysHSI Block sysIO Buffer Programmable Function Unit The Programmable Function Unit (PFU) is the basic building block of the ispXPGA architecture. The PFUs are arranged in rows and columns in the device with PFU (1,1) referring to (row 1, column 1). Each PFU consists of four Configurable Logic Elements (CLEs), four Configurable Sequential Elements (CSEs), and a Wide Logic Generator (WLG). By utilizing these components, the PFU can implement a variety of functions. Table 3 lists some of the function capabilities of the PFU. There are 57 inputs to each PFU and nine outputs. The PFU uses 20 inputs for logic, and 37 inputs drive the control logic from which six control signals are derived for the PFU. Table 3. Function Capability of ispXPGA PFU Function Look-up table Wide logic functions Multiplexing Arithmetic logic Single-port RAM Double-port RAM Shift register LUT-4, LUT-5, LUT-6 Up to 20 input logic functions 2:1, 4:1, 8:1 Dedicated carry chain and booth multiplication logic 16X1, 16X2, 16X4, 32X1, 32X2, 64X1 16X1, 16X2, 32X1 8-bit shift registers (up to 32-bit shift capability) Capability 4 Lattice Semiconductor Figure 2. ispXPGA PFU COUT(r,c) OE PFUCLK0 PFUCLK1 CEB0 CEB1 SR ispXPGA Family Data Sheet OE Control Logic WIN0 WIN1 WIN2 WIN3 CCG IN COUT 4A WLGW0 LUT-4 COUT LUT-4 SUM S3 SYNC/ASYNC D S R Q W0 WIN2 WIN3 WLGW1 D S R CSE0 CLE0 CLK/LE CE Q W1 SEL0 SEL0 XIN0 XIN1 XIN2 CLK/LE CE 4B WLGX0 LUT-4 SEL0 COUT LUT-4 SUM S2 SYNC/ASYNC D D SS R R Q Q X0 IN XIN2 XIN3 Wide Logic Generator WLGX1 D S R CSE1 CLE1 XIN3 CCG CLK/LE CLK/LE CE CE Q X1 SEL1 SEL1 YIN0 YIN1 YIN2 YIN3 CLK/LE CE 4C WLGY0 SYNC/ASYNC LUT-4 COUT LUT-4 SUM S1 D D SS R R Q Q Y0 CCG IN SYNC/ASYNC YIN2 YIN3 WLGY1 D S R CSE2 CLE2 CLK/LE CLK/LE CE CE Q Y1 SEL2 SEL2 ZIN0 ZIN1 ZIN2 CLK/LE CE 4D WLGZ0 LUT-4 COUT LUT-4 SUM S0 SYNC/ASYNC D D SS R R Q Q Z0 IN ZIN2 ZIN3 WLGZ1 D S R CSE3 CLE3 ZIN3 CCG CLK/LE CLK/LE CE CE Q Z1 SEL3 SEL3 CLK/LE CE CIN(r,c) from COUT(r-1,c) 5 Lattice Semiconductor Configurable Logic Element ispXPGA Family Data Sheet The CLE is made up of a four-input Look-up Table (LUT-4), a Carry Chain Generator (CCG), and a two-input AND gate. The LUT-4 creates various combinatorial and memory elements, the CCG creates a single one-bit full adder, and the two-input AND gate can expand the CCG to incorporate Booth Multiplier capability by feeding the output of the AND gate to one of the inputs of the CCG. Of the five inputs that feed each CLE, two are dedicated inputs into each LUT-4 and the remaining three take on varying functionality. The third and fourth inputs can be used as either inputs to the LUT-4 or as a Feed-Thru to the CSE via the WLG. The fifth input can be a data port when the LUT is configured as Distributed Memory, a select line for multiplexer operation, or a Feed-Thru directly to the CSE via the WLG (Figure 2). Look-Up Table - Combinatorial Mode In combinatorial mode, the LUT-4 can implement any logic function up to four inputs. By using the carry chain and the WLG, each LUT-4 can be combined to form the enhanced functions listed in Table 3. Look-Up Table - Distributed Memory Mode In the distributed memory mode, the LUT functions as a memory element. The inputs to the LUT function as Address and Data. Each PFU is capable of implementing up to 64 SRAM bits. Both single and double port RAM can be performed in the PFU (Table 3). Furthermore, the distributed memory can be configured as either synchronous or asynchronous memory. Figure 3 illustrates the LUT while in distributed memory mode. When using any LUT in the PFU in memory mode, the Set/Reset signal will be used for Write Enable (WE(SR)) and the CLK0 signal will be used as the clock for synchronous read and write. Figure 3. LUT in Distributed Memory Mode PFUCLK0 CEB0 WE (SR) ADDR[0] (IN0) ADDR[1] (IN1) ADDR[2] (IN2) ADDR[3] (IN3) DIN (SEL) LUT-4 DOUT (4A) Look-Up Table - Shift Register Mode In the shift register mode, the LUT functions as a 1-bit to 8-bit shift register. This means that each PFU can implement up to four 8-bit shift registers or any cascaded combination. Figure 4 illustrates the LUT when configured in shift register mode. 6 Lattice Semiconductor Figure 4. LUT in Shift Register Mode PFUCLK0 CEB0 ispXPGA Family Data Sheet SEL (SHIFTIN) LUT-4 SHIFTOUT (4A) Carry Chain Generator The Carry Chain Generator is useful for implementing high-speed arithmetic functions. The CCG consists of a twoinput XOR gate whose carryout can be cascaded with the input of the adjacent CCG. As shown in Figure 5, the carryin signal feeds CLE3 of the PFU and is propagated through CLE2 and CLE1 before reaching CLE0. The sum output of the CCG can be fed to the CSE through the WLG. The carryout must propagate to CLE0 for use outside the PFU. The carryout from the PFU can feed the W0 input of CSE0. The CCG also helps to effectively implement wider functions by using its logic elements to expand the capabilities of the LUT-4. Figure 5. Carry Chain Generator COUT(r,c) COUT to CSE0 CLE0 A SUM3 CLE1 B COUT SUM2 CLE2 SUM1 CLE3 CIN SUM SUM0 CIN from Routing COUT(r+1,c) Wide Logic Generator The WLG contains the logic necessary to implement wide gate functions. This is made up of a set of multiplexers that are located between the CLE and the CSE. The WLG helps in enhancing the wide gating capability of the PFU. The outputs of each CLE can be cascaded in the WLG to build wide gating functions. Wide multiplexing functions are also possible with a similar use of the WLG. Figure 6 illustrates the WLG. 7 Lattice Semiconductor Figure 6. ispXPGA Wide Logic Generator COUT WIN2 WIN3 4A S3 SEL0 ispXPGA Family Data Sheet WLGW0 WLGW1 4B XIN2 XIN3 S2 SEL1 WLGX0 WLGX1 SEL3 4C SEL2 4D YIN2 YIN3 S1 WLGY0 WLGY1 ZIN2 ZIN3 S0 WLGZ0 WLGZ1 Configurable Sequential Element There are two registers in each CSE for a total of eight registers in each PFU. This high register count assists in implementing efficient pipelined applications with no utilization penalty. Each register can be configured as a latch or D type flip-flop with either synchronous or asynchronous set or reset. Figure 2 shows the signals that feed the register's D inputs. Feed-through signals in the architecture ensure that registers are efficiently utilized even if the accompanying LUT is occupied. Control Logic The control signals available to the registers in a PFU are Clock, Clock Enable, and Set/Reset. Figure 7 shows the various options available to generate the clock signal. As can be seen, the clock signal is the output of a 12:1 MUX with true and compliment versions available from the 12:1 MUX. Each CSE can chose whether it uses the true or compliment form of the clock. Figure 8 shows the Set/Reset selection for each PFU in the ispXPGA. A common 8 Lattice Semiconductor ispXPGA Family Data Sheet Set/Reset signal controls all the registers for each PFU. This common Set/Reset signal is composed of the logical OR term of the Global Set/Reset signal (GSR) and the selected signal from routing. The polarity of this signal is not controllable inside the PFU. Figure 9 shows the Clock Enable and Output Enable selection for each PFU. Figure 7. Clock Selection per PFU CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 From routing 4 PFUCLK0 PFUCLK1 Figure 8. Set/Reset Selection per PFU 8 From routing Set/Reset GSR Figure 9. Clock Enable and Output Enable Selection per PFU 8 From routing CEB0 8 From routing CEB1 OE Programmable Input/Output Cell The Programmable Input/Output Cell (PIC) is an essential part of the symmetrical architecture of the ispXPGA Family. The PICs interface the PFUs and EBRs to the sysIO and sysHSI blocks of the device. Each PIC contains two Programmable Input/Outputs (PIOs) with a total of 21 inputs and 10 outputs. There are 18 inputs from routing, two inputs from the sysIO buffers, and the Global Set/Reset signal. Four outputs of the PIC connect to routing and two outputs are available as Output Enables for the tri-statable Long Lines. The remaining four outputs feed the sysIO buffers directly (one output enable and one output to each). Each PIC associated with a sysHSI block has four additional inputs and six additional outputs to support the sysHSI blocks. The four additional inputs come from the sysHSI block associated with the PIC. The four of the six additional outputs come from the PIC outputs and feed the sysHSI block, while the remaining two outputs feed routing. Figure 10 shows the block diagram of the PIC with the sysHSI block inputs and outputs. 9 Lattice Semiconductor Figure 10. ispXPGA PIC GSR ispXPGA Family Data Sheet sysIO 9 From routing PIO0 2 From sysHSI block 2 To sysHSI block 2 To routing To routing PIC 2 Only for PICs associated with sysHSI blocks From sysHSI block Only for PICs associated with sysHSI blocks To routing 2 To sysHSI block 9 2 PIO1 To routing From routing sysIO OE1 OE0 Programmable Input/Output The PIO is the building block of a PIC. The PIO has a total of 11 inputs and five outputs. Nine of the 11 inputs are generated from routing. The inputs from routing are the PIO Input (IN), Feed-Thru (FT), Clock (CLK), Input Clock Enable (ICE), Input Set/Reset (ISR), Output Clock Enable (OCEN), Output Set/Reset (OSR), PIO Output Enable (OEN), and PIO Input Enable (IEN). The remaining inputs are the sysIO input buffer signal and the Global Set/ Reset signal. Three of the five outputs (OUT0, OUT1, and OE) feed routing. The last two outputs feed the sysIO buffer directly as the output and output enable of the sysIO output buffer. PIOs associated with sysHSI blocks contain two additional inputs and outputs to support the sysHSI block. The two inputs come from the sysHSI block associated with the PIO, and the two outputs feed the sysHSI block. One of the inputs routes directly through the PIO to routing, while the other is multiplexed with the Feed-Thru, register bypass, and Q output of the register to form the OUT1 output of the PIO. The outputs to the sysHSI block are the same signals as the outputs which feed the sysIO buffers (sysIO Output and sysIO Output Enable). Each PIO has an input register, an output register, and an output enable register as shown in Figure 11. The input register path of the PIO has a `delay' option, which slows the data-flow. A two-input OR function of the Global Set/ Reset (GSR) and Set/Reset (ISR or OSR) signals creates the set/reset term for the respective registers. Each PIO has two pairs of set/reset and clock enable signals. One is exclusive to the input register, whereas the other is common for both the output and output enable registers. The clock (CLK) is common to all registers in a PIO, and the polarity of the clock is controllable. The input, output, and the output enable registers can be configured as a latch or D-type flip-flop. Each PIO is capable of generating an output enable signal, which in turn becomes a PIC output. 10 Lattice Semiconductor Figure 11. ispXPGA PIO Only for PIOs associated with sysHSI Blocks From sysHSI block From sysHSI block Feed-through (FT) From sysIO Input Clock (CLK) Input Clock Enable (ICEN) Input Set/Reset (ISR) Global Set/Reset(GSR) Delay D CLK/LE CE SR Q ispXPGA Family Data Sheet To Routing OUT0 OUT1 To sysIO Output PIO Input (IN) D CLK/LE Q To sysHSI block Output Clock Enable (OCEN) Output Set/Reset (OSR) CE SR Only for PIOs Associated with sysHSI Blocks To sysHSI block To sysIO Output Enable PIO Output Enable(OEN) D CLK/LE CE Q SR PIO Input Enable (IEN) OE VLI Routing Resources The ispXPGA architecture contains a Variable-Length-Interconnect (VLI) routing technology connecting the PFUs, PICs, and EBRs in the device. There are four types of routing resources, Global Lines, Long Lines, General Interconnect, and Local Lines forming the global routing structure. This allows a signal to be routed to any element in the device with the optimal delay. The Global Lines consist of global clock lines and a global set/reset line. These lines are routed to all elements in the device. They are specifically designed for high speed, predictable timing regardless of fan-out. The global clock lines can also be used as dedicated inputs. The Long Lines consist of Horizontal and Vertical Long Lines (HLL and VLL). The VLL and HLL are tri-statable lines spanning the entire device. These lines allow fast routing for high fan-out nets and general-purpose functions. The General Interconnect consists of Double and Deca Lines. The Double Lines connect up to three elements (two plus the driving element), while the Deca Lines connect up to eleven elements (ten plus the driving element). The Local Lines are extremely fast routing paths consisting of Feedback and Direct Connect Lines. The Feedback Lines are internal routing paths from the PFU outputs to the PFU inputs. The Direct Connect Lines connect all adjacent elements. The Common Interface Block (CIB) provides the link between the logic element (PFU, PIC, or EBR) and the VLI Routing resources. The CIB is a switch matrix that can be programmed to connect virtually any routing resource to any input or output of the logic element. 11 Lattice Semiconductor ispXPGA Family Data Sheet Memory The ispXPGA architecture provides a large amount of resources for memory intensive applications. Embedded Block RAMs (EBRs) are available to complement the Distributed Memory that is configured in the PFUs (see LookUp Table -Distributed Memory Mode in the PFU section above). Each memory element can be configured as RAM or ROM. Additionally, the internal logic of the device can be used to configure the memory elements as FIFO and other storage types. These EBRs are referred to as sysMEM blocks. Refer to Table 1 for memory resources per device. sysMEM Blocks The sysMEM blocks are organized in columns distributed throughout the device. Each EBR contains 4.6K bits of dual-port RAM with dedicated control, address, and data lines for each port. Each column of sysMEM blocks has dedicated address and control lines that can be used by each block separately or cascaded to form larger memory elements. The memory cells are symmetrical and contain two sets of identical control signals. Each port has a read/write clock, clock enable, write enable, and output enable. Figure 12 illustrates the sysMEM block. The ispXPGA memory block can operate as single-port or dual-port RAM. Supported configurations are: * * * * 512 x 9 bits single-port 256 x 18 bits single-port 512 x 9 bits dual-port 256 x18 bits dual-port (8 bits data / 1 bit parity) (16 bits data / 2 bits parity) (8 bits data / 1 bit parity) (16 bits data / 2 bits parity) The data widths of "9" and "18" are ideal for applications where parity is necessary. This allows 9 data bits, 8 data bits plus a parity bit, 18 data bits, or 16 data bits plus two parity bits. The logic for generating and checking the parity must be customized separately. Figure 12. sysMEM Block Diagram ADDRA DATAA CLKA ADDRB DATAB CLKB sysMEM Block CEA WEA OEA CEB WEB OEB Read and Write Operations The ispXPGA EBR has fully synchronous read and write operations as well as an asynchronous read operation. These operations allow several different types of memory to be implemented in the device. Synchronous Read: The Clock Enable (CE) and Write Enable (WE) signals control the synchronous read operation. When the CE signal is low, the clock is enabled. When the WE signal is low the read operation begins. Once the address (ADDR) is present, a rising clock edge (or falling edge depending on polarity) causes the stored data to be available on the DATA port. Figure 13 illustrates the synchronous read timing. 12 Lattice Semiconductor Figure 13. EBR Synchronous Read Timing Diagram tEBCPW ispXPGA Family Data Sheet CLK CE WE OE DATA ADDR tEBCES tEBCEH tEBWES tEBWEH Invalid Data tEBOEDIS tEBOEEN tEBWEEN Valid Data tEBWEDIS tEBADDS tEBCO Valid Data tEBADDH Synchronous Write: The WE signal controls the synchronous write operation. When the WE signal is high and the write operation begins. Once the address and data are present and the Output Enable (OE) is active, a rising clock edge (or falling edge depending on polarity) causes the data to be stored into the EBR. Figure 14 illustrates the synchronous write timing. Figure 14. EBR Synchronous Write Timing Diagram CLK tEBPW WE DATA ADDR tEBWES tEBWEH tEBDATAH tEBDATAS tEBADDH tEBADDS WRITE WRITE Asynchronous Read: The WE signal controls the asynchronous read operation. When the WE signal is low, the read operation begins. Shortly after the address is present, the stored data is available on the DATA port. Figure 15 illustrates the asynchronous read timing. For more information about the EBR, refer to Lattice technical note number TN1028 ispXPGA Memory Usage Guidelines, available at www.latticesemi.com. Figure 15. EBR Asynchronous Read Timing Diagram WE OE tEBWEDIS tEBOEDIS tEBOEEN tEBWEEN DATA1 DATA1 Invalid Data DATA ADDR ADDR0 DATA0 tEBARAD_H tEBARADO ADDR1 ADDR2 13 Lattice Semiconductor ispXPGA Family Data Sheet sysCLOCK PLL Description The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) and the various dividers, reset, and feedback signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and generate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are aligned either at the board level or the device level. The ispXPGA devices provide up to eight PLLs. Each PLL receives its input clock from its associated global clock pin, and its output is routed to the associated global clock net. For example, PLL0 receives its clock input from the GCLK0 global clock pin and provides output to the CLK0 global clock net. The PLL also has the ability to output a secondary clock that is a division of the primary clock output. When using the secondary clock, the secondary clock will be routed to the neighboring global clock net. For example, PLL0 will drive its primary clock output on the CLK0 global clock net and its secondary clock output will drive the CLK1 global clock net. Additionally, each PLL has a set of PLL_RST, PLL_FBK, and PLL_LOCK signals. The PLL_RST signal can be generated through routing or a dedicated dual-function I/O pin. The PLL_FBK signal can be generated through a dedicated dual-function I/O pin or internally from the Global Clock net associated with the PLL. The PLL_LOCK signal feeds routing directly from the sysCLOCK PLL circuit. Figure 17 illustrates how the PLL_RST and PLL_FBK signals are generated. Each PLL has four dividers associated with it, M, N, V, and K. The M divider is used to divide the clock signal, while the N divider is used to multiply the clock signal. The V divider allows the VCO frequency to operate at higher frequencies than the clock output, thereby increasing the frequency range. The K divider is only used when a secondary clock output is needed. This divider divides the primary clock output and feeds to the adjacent global clock net. Different combinations of these dividers allow the user to synthesize clock frequencies. Figure 16 shows the ispXPGA PLL block diagram. The PLL also has a delay feature that allows the output clock to be advanced or delayed to improve set-up and clock-to-out times for better performance. This operates by inserting delay on the input or feedback lines of the PLL. For more information on the PLL, please refer to Lattice technical note number TN1003, sysCLOCK PLL Usage and Design Guidelines, available at www.latticesemi.com. Figure 16. ispXPGA PLL Block Diagram Input Clock (M) Divider Programable Delay PLL_RST PLL_LOCK PLL Post-scalar (V) Divider CLK_OUT GCLK_IN Clock Net Feedback Loop (N) Divider PLL_FBK Secondary Clock (K) Divider SEC_OUT Clock Net 14 Lattice Semiconductor Figure 17. ispXPGA PLL_RST and PLL_FBK Generation I/O/PLL_RST ispXPGA Family Data Sheet To PLL From Routing I/O/PLL_FBK To PLL From Clock Net Clock Routing The Global Clock Lines (GCLK) have two sources, their dedicated pins and the sysCLOCK circuit. Figure 18 illustrates the generation of the Global Clock Lines. Figure 18. Global Clock Line Generation From Routing GCLK0 CLK_OUT0 PLL0 SEC_OUT0 From Routing GCLK7 CLK0 CLK7 CLK_OUT7 PLL7 SEC_OUT7 GCLK6 CLK_OUT1 PLL1 SEC_OUT1 From Routing GCLK1 CLK1 CLK6 CLK_OUT6 PLL6 SEC_OUT6 GCLK2 CLK_OUT2 PLL2 SEC_OUT2 From Routing GCLK5 CLK2 CLK5 CLK_OUT5 PLL5 SEC_OUT5 GCLK4 CLK_OUT3 PLL3 SEC_OUT3 CLK3 CLK4 CLK_OUT4 PLL4 SEC_OUT4 GCLK3 sysIO Capability All the ispXPGA devices have eight sysIO banks, where each bank is capable of supporting multiple I/O standards. Each sysIO bank has its own I/O supply voltage (VCCO) and reference voltage (VREF) resources allowing each bank complete independence from the others. Each I/O is individually configurable based on the bank's VCCO and VREF settings. In addition, each I/O has configurable drive strength, weak pull-up, weak pull-down, or a bus-keeper latch. Table 4 lists the number of I/Os supported per bank in each of the ispXPGA devices. Table 5 lists the sysIO standards with the typical values for VCCO, VREF and VTT. The TOE, JTAG TAP pins, PROGRAM, CFG0 and DONE pins of the ispXPGA device are the only pins that do not have the sysIO capabilities. The TOE and CFG0 pins operate off the VCC of the device, supporting only the LVCMOS standard corresponding to the device supply voltage. The TAP pins have a separate supply voltage (VCCJ), which determines the LVCMOS standard corresponding to that supply voltage. There are three classes of I/O interface standards that are implemented in the ispXPGA devices. The first is the unterminated, single-ended interface. It includes the 3.3V LVTTL standard along with the 1.8V, 2.5V, and 3.3V LVCMOS interface standards. Additionally, PCI and AGP-1X are subsets of this type of interface. 15 Lattice Semiconductor ispXPGA Family Data Sheet The second type of interface implemented is the terminated, single-ended interface standard. This group of interfaces includes different versions of SSTL and HSTL interfaces along with CTT, and GTL+. Usage of these particular I/O interfaces requires an additional VREF signal. At the system level a termination voltage, VTT, is also required. Typically an output will be terminated to VTT at the receiving end of the transmission line it is driving. The third type of interface standards are the differential standards LVDS, BLVDS, and LVPECL. The differential standards require two I/O pins to create the differential pair. The logic level is determined by the difference in the two signals. Table 6 lists how these interface standards are implemented in the ispXPGA devices. For more information on sysIO capability, refer to Lattice technical note number TN1000, sysIO Usage Guidelines for Lattice Devices available at www.latticesemi.com. Figure 19. sysIO Banks per Device VCCO6 VCCO7 VREF7 VREF6 GND I/O N GND I/O N I/O 0 I/O 0 I/O 0 Bank 7 Bank 6 I/O N VCCO0 VREF0 GND I/O N I/O 0 VCCO5 VREF5 GND I/O 0 I/O N Bank 0 Bank 5 VCCO1 VREF1 GND I/O N VCCO4 VREF4 GND I/O 0 Bank 1 Bank 4 Bank 2 I/O N Bank 3 I/O N I/O 0 I/O 0 GND VREF2 VCCO2 GND VREF3 VCCO3 Table 4. Number of I/Os per Bank Device XPGA 1200 XPGA 500 XPGA 200 XPGA 125 Max. Number of I/Os per Bank (N) 62 42 26 22 16 Lattice Semiconductor Table 5. ispXPGA Supported I/O Standards sysIO Standard LVTTL LVCMOS-3.3 LVCMOS-2.5 LVCMOS-1.8 PCI AGP-1X SSTL3, Class I, II SSTL2, Class I, II HSTL, Class I HSTL, Class III GTL+ LVPECL LVDS 1 ispXPGA Family Data Sheet VCCO 3.3V 3.3V 2.5V 1.8V 3.3V 3.3V 3.3V 2.5V 1.5V 1.5V N/A 3.3V 2.5V 2.5V VREF N/A N/A N/A N/A N/A N/A 1.5V 1.25V 0.75V 0.9V 1.0V N/A N/A N/A VTT N/A N/A N/A N/A N/A N/A 1.5V 1.25V 0.75V 1.5V 1.5V N/A N/A N/A BLVDS 1. VCCO must be 2.5V for high speed serial operations (sysHSI block). Table 6. Differential Interface Standard Support1 sysIO Buffer Not Using sysHSI Block LVDS BLVDS LVPECL Driver Receiver Driver Receiver Driver Receiver Supported with external resistor network Supported with standard termination Supported with external resistor network Supported (may need termination) Supported with external resistor network Supported with termination sysIO Buffer Using sysHSI Block Supported Supported with standard termination Not supported Supported (may need termination) Not supported Supported with termination 1. For more information, refer to Lattice technical note TN1000, sysIO Usage Guidelines, available at www.latticesemi.com. 17 Lattice Semiconductor ispXPGA Family Data Sheet High Speed Serial Interface Block (sysHSI Block) The High Speed Serial Interface (sysHSI) allows high speed serial data transfer over a pair of LVDS I/O. The ispXPGA devices have multiple sysHSI blocks. Each sysHSI block has two SERDES blocks which contain two main sub-blocks, Transmitter (with a serializer) and Receiver (with a deserializer) including Clock/Data Recovery Circuit (CDR). Each SERDES can be used as a full duplex channel. The two SERDES in sysHSI blocks share a common clock and must operate at the same nominal frequency. Figure 20 shows the sysHSI block. Device features support two data coding modes: 10B/12B and 8B/10B (for use with other encoding schemes, see Lattice's sysHSI technical notes). The encoding and decoding of the 10B/12B standard are performed within the sysHSI block. For the 8B/10B standard, the symbol boundaries are aligned internally but the encoding and decoding are performed outside the sysHSI block. Each SERDES block receives a single high speed serial data input stream (with embedded clock) from an input, and provide a low speed 10-bit wide data stream and a recovered clock to the device. For transmitting, SERDES converts a 10-bit wide low-speed data stream to a single high-speed data stream with embedded clock for output. Additionally, multiple sysHSI blocks can be grouped together to form a source synchronous interface of 1-10 channels. Table 7 shows the clock sources available for the REFCLKs of the different sysHSI blocks. The Signal Description table in this data sheet provides the descriptions of the sysHSI block inputs and outputs. For more information on the SERDES/CDR, refer to Lattice technical note number TN1020, sysHSI Usage Guidelines. Figure 20. sysHSI Block Diagram SERDES(HSI#A) Serializer SOUT 10 TXD From PICs SIN 10 RXD To PICs To PICs To PICs To PICs To PICs From PICs From PICs From PICs To PICs From Global Clock Tree RECCLK Deserializer and Clock/Data Recovery sysIO CDRLOCK LOSS SYDT EXLOSS CDRRST CAL Shared Source Synchronous Pins Drive Multiple sysHSI blocks SS_CLKOUT SS_CLKIN CSLOCK CSPLL REFCLK EXLOSS CDRRST SYDT LOSS From PICs From PICs To PICs To PICs To PICs To PICs To PICs Deserializer and Clock/Data Recovery SIN CDRLOCK RECCLK 10 RXD SOUT Serializer SERDES(HSI#B) 10 TXD From PICs 18 Lattice Semiconductor Table 7. sysHSI Block REFCLK Selections1 sysHSI Block 0 1 2 3 4 5 6 7 8 9 ispXPGA Family Data Sheet Available Global Clock Nets CLK0, CLK1, CLK2, CLK3 CLK0, CLK1, CLK2, CLK4 CLK0, CLK1, CLK2, CLK5 CLK0, CLK1, CLK3, CLK6 CLK0, CLK1, CLK3, CLK7 CLK0, CLK3, CLK5, CLK7 CLK0, CLK2, CLK5, CLK7 CLK0, CLK1, CLK5, CLK6 CLK0, CLK5, CLK6 CLK0, CLK5, CLK6, CLK7 1. Table 6 applies to all devices. Ignore sysHSI blocks not available in a specific device. Configuration and Programming The ispXPGA family of devices takes a unique approach to FPGA configuration memory. It contains two types of memory, Static RAM and non-volatile E2CMOS cells. The static RAM is used to control the functionality of the device during normal operation and the E2CMOS memory cells are used to load the SRAM. The E2CMOS memory module can be thought of as the hard drive for the ispXPGA configuration and the SRAM as the working configuration memory. There is a one-to-one relationship between SRAM memory and the E2CMOS cells. The SRAM can be configured either from the E2CMOS memory or from an external source, as shown in Figure 21. Figure 21 shows the different ports and modes that are used in the configuration and programming of the ispXPGA devices. There are two possible ports that can be used for configuration of the SRAM memory: the ISP port which is compliant to the IEEE 1149.1 Test Access Port (TAP) Std. and the ISP port which accommodates bit-wide configuration. The sysCONFIG port allows byte-wide configuration of the SRAM configuration memory. When programming the E2CMOS memory, only the 1149.1 TAP can be used. Configuration and programming done through the 1149.1 Test Access Port (TAP) are fully compliant to both the IEEE Std. 1149.1 Boundary Scan TAP specification and the IEEE Std. 1532 In-System Configuration specification. To configure or program the device using the 1149.1 TAP the device must be in the ISP mode. To configure the SRAM memory using the sysCONFIG Port, the device must be in the sysCONFIG mode. Upon power-up, the device's SRAM memory can be configured either from the E2CMOS memory or from an external source through the sysCONFIG mode. Additionally, the SRAM can be re-configured from the E2CMOS memory by executing a "REFRESH." See Lattice technical note number TN1026, ispXP Configuration Usage Guide, for more in depth information on the different programming modes, timing and wake-up, available at www.latticesemi.com. 19 Lattice Semiconductor Figure 21. ispXP Block Diagram ISP 1149.1 TAP Port Port ispXPGA Family Data Sheet sysCONFIG Peripheral Port ISP Mode BACKGND 1532 sysCONFIG Programming in seconds Configuration in milliseconds Power-up E2CMOS Memory Space Memory Space Refresh Download in microseconds SRAM Memory Space IEEE 1149.1-Compliant Boundary Scan Testability All ispXPGA devices have boundary scan cells and are compliant with the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic notes. Internal boundary scan registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked into a board-level serial scan path for more board level testing. Security Scheme A programmable security scheme is provided on the ispXPGA devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, the security scheme prevents read-back of the programmed pattern by a device programmer, securing proprietary designs from competitors. The entire device must be erased in order to erase the security scheme. Density Shifting The ispXPGA family has been designed to ensure that different density devices in the same package have the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization will impact the likely success in each case. 20 Lattice Semiconductor ispXPGA Family Data Sheet Absolute Maximum Ratings1, 2, 3 1.8V 2.5V/3.3V Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V PLL Supply Voltage (VCCP) . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V Output Supply Voltage (VCCO) . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V IEEE 1149.1 TAP Supply Voltage (VCCJ) . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V Input Voltage Applied4 . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -65 to 150C. . . . . . . . . -65 to 150C Junction Temperature (TJ) with Power Applied . . -55 to 150C. . . . . . . . . -55 to 150C 1. Stress above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied (while programming, following the programming specifications). 2. Compliance with the Lattice Thermal Management technical note is required. 3. All voltages referenced to GND. 4. Overshoot and undershoot of -2V to (VIH (MAX) + 2) volts is permitted for a duration of <20ns Recommended Operating Conditions Symbol Supply Voltage for 1.8V device VCC Supply Voltage for 2.5V device Supply Voltage for 3.3V device Supply Voltage for PLL block for 1.8V device VCCP Supply Voltage for PLL block for 2.5V device Supply Voltage for PLL block for 3.3V device Supply Voltage for IEEE 1149.1 Test Access Port for LVCMOS 1.8V VCCJ TJ (COM) TJ (IND) Supply Voltage for IEEE 1149.1 Test Access Port for LVCMOS 2.5V Supply Voltage for IEEE 1149.1 Test Access Port for LVCMOS 3.3V Junction Temperature Commercial Operation Junction Temperature Industrial Operation Parameter Min 1.65 2.3 3.0 1.65 2.3 3.0 1.65 2.3 3.0 0 -40 Max 1.95 2.7 3.6 1.95 2.7 3.6 1.95 2.7 3.6 85 105 Units V V V V V V V V V C C E2CMOS Erase Reprogram Specifications Parameter Erase/Reprogram Cycle 1 Min 1,000 Max -- Units Cycles 1. Valid over commercial temperature range. Hot Socketing Characteristics1, 2, 3, 4 Symbol IDK 1. 2. 3. 4. Parameter Input or I/O Leakage Current Condition 0 VIN 3.0V Min -- Typ +/-50 Max +/-800 Units A Insensitive to sequence of VCC and VCCO. However, assumes monotonic rise / fall rates for VCC and VCCO. LVTTL, LVCMOS only 0 < VCC VCC (MAX), 0 < VCCO VCCO (MAX) IDK is additive to IPU, IPD or IBH. Device defaults to pull-up until fuse circuitry is active. 21 Lattice Semiconductor ispXPGA Family Data Sheet DC Electrical Characteristics Over Recommended Operating Conditions Symbol IIL, IIH1 IPU IPD IBHLS IBHHS IBHLO IBHHO VBHT C1 C2 C3 Parameter Input or I/O Low Leakage I/O Active Pull-up Current I/O Active Pull-down Current Condition 0 VIN < (VCCO - 0.2V) (VCCO - 0.2V) VIN 3.6V 0 VIN 0.7 VCCO VIL (MAX) VIN VIH (MAX) Min -- -- 30 30 30 30 -- -- VCCO * 0.35 VCCO = 3.3V, 2.5V, 1.8V VCC = 1.8V, VIO = 0 to VIH (MAX) VCCO = 3.3V, 2.5V, 1.8V VCC = 1.8V, VIO = 0 to VIH (MAX) VCCO = 3.3V, 2.5V, 1.8V VCC = 1.8V, VIO = 0 to VIH (MAX) -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- 8 6 6 Max 10 40 150 150 -- -- 150 150 VCCO * 0.65 -- -- -- -- -- -- Units A A A A A A A A V pf pf pf Bus Hold Low Sustaining Current VIN = VIL (MAX) Bus Hold High Sustaining Current VIN = 0.7 VCCO Bus Hold Low Overdrive Current Bus Hold Trip Points I/O Capacitance2 Clock Capacitance2 Global Input Capacitance2 0 VIN VIH (MAX) Bus Hold High Overdrive Current 0 VIN VIH (MAX) 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. TA = 25C, f = 1.0MHz. Supply Current Over Recommended Operating Conditions Symbol ICC1, 2 Parameter Standby Core Operating Power Supply Current Condition VCC = 3.3V VCC = 2.5V VCC = 1.8V VCCO = 3.3V ICCO3 Standby Output Power Supply Current VCCO = 2.5V VCCO = 1.8V VCCO = 1.5V VCCP = 3.3V ICCP4 Standby PLL Operating Supply Current VCCP = 2.5V VCCP = 1.8V VCCJ = 3.3V ICCJ5 Standby IEEE 1149.1 TAP Power Supply Current VCCJ = 2.5V VCCJ = 1.8V Min -- -- -- -- -- -- -- -- -- -- -- -- -- Typ 220 220 200 2.0 2.0 2.0 2.0 17.0 17.0 15.0 2.0 1.5 1.0 Max -- -- -- -- -- -- -- -- -- -- -- -- -- Units mA mA mA mA mA mA mA mA mA mA mA mA mA 1. TA = 25C, frequency = 1.0 MHz, device configured with 16-bit counters. 2. ICC varies with specific device configuration and operating frequency. For more accurate power calculation use the ispXPGA Power Estimator. 3. TA = 25C, per bank, no DC load, frequency = 0 MHz. 4. TA = 25C, per PLL, frequency = 10 MHz. 5. TA = 25C 22 Lattice Semiconductor ispXPGA Family Data Sheet sysIO Recommended Operating Conditions VCCO (V)1 Standard LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.82 LVTTL PCI 3.3 AGP-1X SSTL 2 SSTL 3 CTT 3.3 CTT 2.5 HSTL Class I HSTL Class III GTL+ LVDS LVPECL BLVDS Min. 3.0 2.3 1.65 3.0 3.0 3.15 2.3 3.0 3.0 2.3 1.4 1.4 2.3 3.0 2.3 Typ. 3.3 2.5 1.8 3.3 3.3 3.3 2.5 3.3 3.3 2.5 1.5 1.5 2.5 3.3 2.5 Max. 3.6 2.7 1.95 3.6 3.6 3.45 2.7 3.6 3.6 2.7 1.6 1.6 2.7 3.6 2.7 Min. 1.15 1.3 1.35 1.35 0.68 0.882 VREF (V) Typ. 1.25 1.5 1.5 1.5 0.75 0.9 1.0 Max. 1.35 1.7 1.65 1.65 0.9 1.122 - 1. Inputs independent of VCCO. 2. Design tool default setting. 23 Lattice Semiconductor ispXPGA Family Data Sheet sysIO DC Electrical Characteristics Over Recommended Operating Conditions VIL Standard LVCMOS 3.3 Min. (V) -0.3 Max. (V) 0.8 Min. (V) 2.0 VIH Max. (V) 3.6 VOL Max. (V) 0.4 0.2 LVCMOS 2.5 -0.3 0.7 0.683 LVCMOS 1.81 -0.3 0.35VCC 0.8 1.08 3 VOH Min. (V) VCCO - 0.4 VCCO - 0.2 VCCO - 0.4 VCCO - 0.2 VCCO - 0.4 VCCO - 0.2 VCCO - 0.4 VCCO - 0.2 0.9 VCCO 0.9 VCCO VCCO - 1.1 VCCO - 0.9 VCCO - 0.62 VCCO - 0.43 VREF + 0.4 VREF + 0.4 VCCO - 0.4 VCCO - 0.4 N/A IOL (mA) IOH (mA) 20, 16, 12, -20, -16,-12, 8, 5.33, 4 -8, -5.33, -4 0.1 16, 12, 8, 5.33, 4 0.1 12, 81, 5.33, 4 0.1 -0.1 -16, -12, -8, -5.33, -4 -0.1 -12, -81, -5.33, -4 -0.1 1.7 1.073 0.65VCC 2.0 1.5 3 3.6 0.4 0.2 3.6 0.4 0.2 LVTTL -0.3 3.6 0.4 0.2 20, 16, 12, -20, -16,-12, 8, 5.33, 4 -8, -5.33, -4 0.1 1.5 1.5 8 16 7.6 15.2 8 8 8 24 36 -0.1 -0.5 -0.5 -8 -16 -7.6 -15.2 -8 -8 -8 -8 N/A PCI 3.3 AGP-1X SSTL 3 Class I SSTL 3 Class II SSTL 2 Class I SSTL 2 Class II CTT 3.3 CTT 2.5 HSTL Class I HSTL Class III GTL+ -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 0.3VCCO 1.083 0.3 VCCO VREF - 0.2 VREF - 0.2 0.5 VCCO 1.53 0.5 VCCO VREF + 0.2 VREF + 0.2 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 0.1 VCCO 0.1 VCCO 0.7 0.5 0.54 0.35 VREF - 0.4 VREF - 0.4 0.4 0.4 0.6 VREF - 0.18 VREF + 0.18 VREF - 0.18 VREF + 0.18 VREF - 0.2 VREF - 0.2 VREF - 0.1 VREF - 0.1 VREF - 0.2 VREF + 0.2 VREF + 0.2 VREF + 0.1 VREF + 0.1 VREF + 0.2 1. Design tool default setting. 2. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND connections or between the last GND in a bank and the end of a bank 3. Applicable for ispXPGA V/B devices. 24 Lattice Semiconductor ispXPGA Family Data Sheet sysIO Differential Standards DC Electrical Characteristics Parameter LVDS VTHD VCM IIN VOH VOL VOD VOD VOS VOS IOSD BLVDS1 VINP, VINM VTHD VCM IIN VOH VOL VOD VOD VOS VOS IOSD Input voltage Differential input threshold Input Common Mode voltage Input current Output High Voltage for VOP or VOM Output Low Voltage for VOP or VOM Output Voltage Differential Change in VOD Between H and L Output Voltage Offset Change in VOS Between H and L Output Short Circuit Current VOD = 0. Driver Outputs Shorted. 36mA |VOP + VOM| /2, RT = 27 1.1V 1.3V Half the sum of the two inputs Power on or Power off RT = 27 RT = 27 |VOP - VOM|, RT = 27 0V +/-100mV 0.05V -- -- 0.95V 240mV -- -- -- -- 1.4V 1.1V 300mV 2.4V -- 2.35V +/-10uA 1.80V -- 460mV 27mV 1.5V 27mV 65mA 1 Description Input voltage Differential input threshold Input Common Mode voltage Input current Output High Voltage for VOP or VOM Output Low Voltage for VOP or VOM Output Voltage Differential Change in VOD between high and low Output Voltage Offset Change in VOS between H and L Output short circuit current Test Conditions Min. 0V +/-100mV Typ. -- -- -- -- 1.38V 1.03V 350mV -- 1.25V -- -- Max. 2.4V -- 2.35V +/-10uA 1.60V -- 450mV 50mV 1.375V 50mV 24mA VINP, VINM Half the sum of the two inputs Power on or Power off RT = 100 Ohm RT = 100 Ohm |VOP - VOM|, RT = 100 ohm |VOP + VOM|/2, RT = 100 ohm VOD = 0V Driver outputs shorted 0.05V -- -- 0.9V 250mV -- 1.125V -- -- 1. VOP and VOM are the two outputs of the LVDS/BLVDS output buffer. LVPECL1 DC Parameter VCCO VIH VIL VOH VOL VDIFF Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low Differential Input voltage 1.49 0.86 1.8 0.96 0.3 Parameter Description Min. 3.0 2.72 2.125 2.11 1.27 -- 1.49 0.86 1.92 1.06 0.3 Max. Min. 3.3 2.72 2.125 2.28 1.43 -- 1.49 0.86 2.13 1.3 0.3 Max. Min. 3.6 2.72 2.125 2.41 1.57 -- Max. Units V V V V V V 1. These values are valid at the output of the source termination pack as shown above with 100-ohm differential load only (see Figure 22). The VOH levels are 200mV below the standard LVPECL levels and are compatible with devices tolerant of the lower common mode ranges. 25 Lattice Semiconductor Figure 22. LVPECL Driver with Three Resistor Pack ispXPGA LVPECL Buffer 1/4 of Bourns P/N CAT 16-PC4F12 A Rs Zo ispXPGA Family Data Sheet to LVPECL differential receiver Rs Zo ispXPGA External Switching Characteristics Over Recommended Operating Conditions -4 Parameter tCO tS tH tSINDLY tHINDLY tCOPLL tSPLL tHPLL tSINDLYPLL tHINDLYPLL Description Global Clock Input Setup Global Clock Input Hold Global Clock Input Setup Global Clock Input Hold Conditions PIO Input Register without input delay PIO Input Register without input delay PIO Input Register with input delay PIO Input Register with input delay PIO Input Register without input delay using PLL without delay PIO Input Register without input delay using PLL without delay PIO Input Register with input delay using PLL without delay PIO Input Register with input delay using PLL without delay Min. -- -2.7 4.6 3.8 0.0 -- 1.1 0.8 7.6 -4.6 Max. 7.1 -- -- -- -- 3.3 -- -- -- -- Min. -- -2.3 5.3 4.4 0.0 -- 1.3 1.0 8.8 -4.0 Global Clock Input to Output PIO Output Register -3 Max. Units 8.2 -- -- -- -- 3.8 -- -- -- -- ns ns ns ns ns ns ns ns ns Global Clock Input to Output PIO Output Register using PLL without delay Global Clock Input Setup Global Clock Input Hold Global Clock Input Setup Global Clock Input Hold 26 RT=100 RD Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA PFU Timing Parameters Over Recommended Operating Conditions -4 Parameter Functional Delays Description Min. Max. Min. -3 Max. Units LUTs tLUT4 tLUT5 tLUT6 tLSR_S tLSR_H tLSR_CO tLCTHRUR tLCTHRUL1 tLSTHRU tLSINCOUT tLCINSOUTR tLCINSOUTL 4-Input LUT Delay 5-Input LUT Delay 6-Input LUT Delay Shift Register Setup Time Shift Register Hold Time Shift Register Clock to Output Delay MC (Macro Cell) Carry In to MC Carry Out Delay (Ripple) MC Carry In to MC Carry Out Delay (Look Ahead) MC Sum In to MC Sum Out Delay MC Sum In to MC Carry Out Delay MC Carry In to MC Sum Out Delay (Ripple) MC Carry In to MC Sum Out Delay (Look Ahead) PFU Feed-Thru Delay Clock to RAM Output Address Setup Time Data Setup Time Write Enable Setup Time Address Hold Time Data Hold Time Write Enable Hold Time Clock Pulse Width (High or Low) Address to Output Delay -- -- -- -0.62 0.63 -- -- -- -- -- -- -- -- -- -0.40 0.22 0.46 0.60 0.11 0.12 3.00 -- 0.44 0.79 0.93 -- -- 0.75 0.09 0.05 0.45 0.31 0.39 0.28 0.16 1.33 -- -- -- -- -- -- -- 0.93 -- -- -- -0.53 0.72 -- -- -- -- -- -- -- -- -- -0.34 0.25 0.53 0.69 0.13 0.14 3.45 -- 0.51 0.91 1.07 -- -- 0.86 0.10 0.06 0.52 0.36 0.45 0.32 0.18 1.53 -- -- -- -- -- -- -- 1.07 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Shift Register (LUT) Arithmetic Functions Feed-thru tLFT tLRAM_CO tLRAMAD_S tLRAMD_S tLRAMWE_S tLRAMAD_H tLRAMD_H tLRAMWE_H tLRAMCPW tLRAMADO Distributed RAM Register/Latch Delays Registers tL_CO tL_S tL_H tLCE_S tLCE_H Register Clock to Output Delay Register Setup Time (Data before Clock) Register Hold Time (Data after Clock) Register Clock Enable Setup Time Register Clock Enable Hold Time Latch Gate to Output Delay Latch Setup Time Latch Hold Time Latch Propagation Delay (Transparent Mode) -- 0.14 -0.12 -0.11 0.11 -- 0.14 -0.12 -- 0.62 -- -- -- -- 0.10 -- -- 0.10 -- 0.16 -0.10 -0.09 0.13 -- 0.16 -0.10 -- 0.71 -- -- -- -- 0.12 -- -- 0.12 ns ns ns ns ns ns ns ns ns Latches tL_GO tLL_S tLL_H tLLPD 27 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA PFU Timing Parameters (Continued) Over Recommended Operating Conditions -4 Parameter Description Asynchronous Set/Reset to Output Asynchronous Set/Reset Pulse Width Asynchronous Set/Reset Recovery Synchronous Set/Reset Setup Time Synchronous Set/Reset Hold Time Min. -- -- -- -0.03 0.03 Max. 1.17 4.50 0.55 -- -- Min. -- -- -- -0.03 0.03 -3 Max. 1.35 5.18 0.63 -- -- Units ns ns ns ns ns Timing v.2.0 Reset/Set tLASSRO tLASSRPW tLASSRR tLSSR_S tLSSR_H 1. tLCTHRUL quoted bit by bit. ispXPGA PIC Timing Parameters -4 Parameter Register/Latch Delays tIO_CO tIO_S tIO_H tIOCE_S tIOCE_H tIO_GO tIOL_S tIOL_H tIOLPD tIOASRO tIOASRPW tIOASRR tIOBUF tIOIN tIOEN tIODIS tIOFT Register Clock to Output Delay Register Setup Time (Data before Clock) Register Hold Time (Data after Clock) Register Clock Enable Setup Time Register Clock Enable Hold Time Latch Gate to Output Delay Latch Setup Time Latch Hold Time Latch Propagation Delay (Transparent Mode) Asynchronous Set/Reset to Output Asynchronous Set/Reset Pulse Width Asynchronous Set/Reset Recovery Time Output Buffer Delay Input Buffer Delay Output Enable Delay Output Disable Delay Feed-thru Delay -- 0.05 0.06 -0.03 0.13 -- 0.05 0.06 -- -- -- -- -- -- -- -- -- 1.09 -- -- -- -- 0.91 -- -- 0.10 1.26 4.50 0.25 1.06 0.76 0.56 -0.10 0.20 -- 0.06 0.07 -0.03 0.15 -- 0.06 0.07 -- -- -- -- -- -- -- -- -- 1.25 -- -- -- -- 1.05 -- -- 0.12 1.45 5.18 0.29 1.22 0.87 0.64 -0.09 0.23 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Timing v.2.0 -3 Max. Min. Max. Units Description Min. Input/Output Delays 28 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA EBR Timing Parameters -4 Parameter Synchronous Write tEBSWAD_S tEBSWAD_H tEBSWCPW tEBSWWE_S tEBSWWE_H tEBSWD_S tEBSWD_H Synchronous Read tEBSR_CO tEBSRAD_S tEBSRAD_H tEBSRCPW tEBSRCE_S tEBSRCE_H tEBSRWE_S tEBSRWE_H tEBSRWEEN tEBSRWEDIS tEBSREN tEBSRDIS tEBARADO tEBARAD_H tEBARWEEN tEBARWEDIS tEBAREN tEBARDIS Clock to Data Delay Address Setup Delay Address Hold Delay Clock Pulse Width Clock Enable Setup Time Clock Enable Hold Time Write Enable Setup Time Write Enable Hold Time Write Enable to Data Enable Time Write Enable to Data Disable Time Output Enable to Data Enable Time Output Enable to Data Disable Time Address to New Valid Data Delay Address to Previous Valid Data Delay Write Enable to Data Enable Time Write Enable to Data Disable Time Output Enable to Data Enable Time Output Enable to Data Disable Time -- 0.10 -0.07 -- -1.71 1.69 -0.17 0.12 -- -- -- -- -- -- -- -- -- -- 2.19 -- -- 3.40 -- -- -- -- 1.05 1.02 1.05 0.86 2.46 2.17 1.04 1.01 1.05 0.86 -- 0.12 -0.06 -- -1.45 1.94 -0.14 0.14 -- -- -- -- -- -- -- -- -- -- 2.52 -- -- 3.91 -- -- -- -- 1.21 1.17 1.21 0.99 2.83 2.50 1.20 1.16 1.21 0.99 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Timing v.2.0 -3 Max. -- -- 3.40 -- -- -- -- Min. 0.70 -0.33 -- -0.10 0.18 0.32 -0.22 Max. -- -- 3.91 -- -- -- -- Units ns ns ns ns ns ns ns Description Address Setup Delay Address Hold Delay Clock Pulse Width Write Enable Setup Time Write Enable Hold Time Data Setup Time Data Hold Time Min. 0.61 -0.39 -- -0.12 0.16 0.28 -0.26 Asynchronous Read 29 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Family Timing Adders Parameter Optional Adders tINDIO tIOI Input Adjusters LVTTL_in LVCMOS_18_in LVCMOS_25_in LVCMOS_33_in AGP_1X_in CTT25_in CTT33_in GTL+_in HSTL_I_in HSTL_III_in LVDS_in BLVDS_in LVPECL_in PCI_in SSTL2_I_in SSTL2_II_in SSTL3_I_in SSTL3_II_in tIOO Output Adjusters Slow Slew LVTTL_out LVCMOS_18_4mA_out Using Slow Slew (LVTTL and tIOBUF, tIOEN LVCMOS Outputs only) Using 3.3V TTL Drive Using 1.8V CMOS Standard, 4mA Drive tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS -- -- -- -- -- -- -- -- -- -- -- 0.7 1.0 0.8 0.6 0.0 0.2 0.7 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- 0.7 1.0 0.8 0.6 0.0 0.2 0.7 0.5 0.5 0.5 0.5 ns ns ns ns ns ns ns ns ns ns ns Using 3.3V TTL Using 1.8V CMOS Using 2.5V CMOS Using 3.3V CMOS Using AGP 1x Using CTT 2.5V Using CTT 3.3V Using GTL+ Using HSTL 2.5V, Class I Using HSTL 2.5V, Class III Using Low Voltage Differential Signaling (LVDS) tIOIN tIOIN tIOIN tIOIN tIOIN tIOIN tIOIN tIOIN tIOIN tIOIN tIOIN -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.5 0.0 0.3 0.5 1.0 1.0 1.0 0.5 0.5 0.5 0.8 0.8 0.8 1.0 0.8 0.5 0.8 0.8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.5 0.0 0.3 0.5 1.0 1.0 1.0 0.5 0.5 0.5 0.8 0.8 0.8 1.0 0.8 0.5 0.8 0.8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Input Delay -- -- 6.0 -- 6.9 ns Description Base Parameter -4 Min. Max. Min. -3 Max. Units Using Bus Low Voltage tIOIN Differential Signaling (BLVDS) Using Low Voltage PECL Using PCI Using SSTL 2.5V, Class I Using SSTL 2.5V, Class II Using SSTL 3.3V, Class I Using SSTL 3.3V, Class II tIOIN tIOIN tIOIN tIOIN tIOIN tIOIN LVCMOS_18_5.33mA_out Using 1.8V CMOS Standard, 5.33mA Drive LVCMOS_18_8mA_out LVCMOS_18_12mA_out LVCMOS_25_4mA_out Using 1.8V CMOS Standard, 8mA Drive Using 1.8V CMOS Standard, 12mA Drive Using 2.5V CMOS Standard, 4mA Drive LVCMOS_25_5.33mA_out Using 2.5V CMOS Standard, 5.33 mA Drive LVCMOS_25_8mA_out LVCMOS_25_12mA_out LVCMOS_25_16mA_out Using 2.5V CMOS Standard, 8mA Drive Using 2.5V CMOS Standard, 12mA Drive Using 2.5V CMOS Standard, 16mA Drive 30 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Family Timing Adders (Continued) Parameter LVCMOS_33_4mA_out Description Using 3.3V CMOS Standard, 4mA Drive Base Parameter tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS -4 Min. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 1.0 1.0 0.7 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 1.0 1.0 1.0 0.5 0.5 0.5 0.5 0.5 Min. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -3 Max. 1.0 1.0 0.7 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 1.0 1.0 1.0 0.5 0.5 0.5 0.5 0.5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Timing v.2.0 LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard, 5.33mA Drive LVCMOS_33_8mA_out LVCMOS_33_12mA_out LVCMOS_33_16mA_out LVCMOS_33_24mA_out AGP_1X_out CTT25_out CTT33_out GTL+_out HSTL_I_out HSTL_III_out LVDS_out BLVDS_out LVPECL_out PCI_out SSTL2_I_out SSTL2_II_out SSTL3_I_out SSTL3_II_out Using 3.3V CMOS Standard, 8mA Drive Using 3.3V CMOS Standard, 12mA Drive Using 3.3V CMOS Standard, 16mA Drive Using 3.3V CMOS Standard, 24mA Drive Using AGP 1x Standard Using CTT 2.5V Using CTT 3.3V Using GTL+ Using HSTL 2.5V, Class I Using HSTL 2.5V, Class III Using Low Voltage Differential Signaling (LVDS) Using Bus Low Voltage Differ- tIOBUF, tIOEN, tIODIS ential Signaling (BLVDS) Using Low Voltage PECL Using PCI Standard Using SSTL 2.5V, Class I Using SSTL 2.5V, Class II Using SSTL 3.3V, Class I Using SSTL 3.3V, Class II tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS tIOBUF, tIOEN, tIODIS 31 Lattice Semiconductor ispXPGA Family Data Sheet sysHSI Block Timing Figure 23 provides a graphical representation of the SERDES receiver input requirements. It provides guidance on a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and N input skew tolerance. Figure 23. Receive Data Eye Diagram Template (Differential) BIT TIME VLVDT = 200mV 1.2 V JTTH JTTH : Optimum Threshold Crossing Jitter EOSIN JTTH The data pattern eye opening at the receive end of a link is considered the ultimate measure of received signal quality. Almost all detrimental characteristics of a transmit signal and the interconnection link design result in eye closure. This combined with the eye-opening limitations of the line receiver can provide a good indication of a link's ability to transfer error-free data. Signal jitter is of special interest to system designers. It is often the primary limiting characteristic of long digital links and of systems with high noise level environments. An interesting characteristics of the clock and data recovery (CDR) portion of the ispXPGA SERDES receiver is its ability to filter incoming signal jitter that is below the clock recovery PLL bandwidth. For signals with high levels of low frequency jitter, the receiver can detect incoming data error free, with eye openings significantly less than that shown in Figure 23. sysHSI Block AC Specifications Operating Frequency Ranges Symbol fCLK Description REFCLK, SS_CLKIN, SS_CLKOUT Mode All SS: no CAL fSIN Serial Input SS: CAL 10B12B 8B10B fSOUT Serial Out LVDS with eoSIN with eoSIN with eoSIN with eoSIN CL=5 pF, RL=100 Ohm Test Condition Min 40 400 400 400 400 400 Max 250 7501 800 850 1 Unit MHz Mbps Mbps Mbps Mbps Mbps 8501 1 850 1. These max. numbers apply to the -4 speed grade only. For the -3 speed grade, the corresponding numbers are: SS: no CAL 650 SS: CAL 700 10B12B 800 8B10B 800 32 Lattice Semiconductor LOCKIN Time Symbol tSCLOCK tCDRLOCK tSYNC tCAL tSUSYNC tHDSYNC Description CSPLL Lock Time CDRPLL Lock-in Time SyncPat Length CAL Duration SyncPat Set-up Time to CAL SyncPat Hold Time from CAL Mode All SS 10B12B 8B10B SS SS SS SS ispXPGA Family Data Sheet Condition After Input is Stabilized With SS mode Sync Pattern With 10B12B Sync Pattern With 8B10B Idle Pattern Min. -- -- -- -- 1200 1100 50 50 Max. 25 1024 1024 480 -- -- -- -- Units S tRCP1 tRCP tRCP tRCP tRCP tRCP tRCP 1. REFCLK clock period. REFCLK and SS_CLKIN Timing Symbol fDREFCLK tJPPREFCLK tPWREFCLK tRFREFCLK Description Frequency Deviation Between TX REFCLK and CDRX REFCLK on one link. REFCLK, SS_CLKIN Peak-to-Peak Period Jitter REFCLK, SS_CLKIN Pulse Width, (80% to 80% or 20% to 20%). REFCLK, SS_CLKIN Rise/Fall Time. (20% to 80% or 80% to 20%) Mode 8B10B, 10B12B All All All 40-250 (MHz) Condition Min. -100 -0.005 1 -- Max. 100 0.005 -- 2 Units ppm UIPP ns ns SERIALIZER Timing1 Symbol tJPPSOUT tJPP8B10B tRFSOUT tCOSOUT tSKTX tCKOSOUT Description SOUT Peak-to-Peak Output Data Jitter SOUT Peak-to-Peak Random Jitter SOUT Peak-to-Peak Deterministic Jitter SOUT Output Data Rise/Fall Time (20%, 80%) REFCLK to SOUT Delay Skew of SOUT with Respect to SS_CLKOUT SS_CLKOUT to bit0 of SOUT Mode All 8B10B 8B10B LVDS BLVDS SS/8B10B 10B12B SS SS All All Note 3 Note 3 900 Mbps w/k28.7900 Mbps w/k28.5+ Condition Min. -- -- -- -- -- 2Bt2 + 2 1Bt + 2 -- 2 Max. 0.25 130 110 700 900 2Bt2 + 10 1Bt + 10 250 2 Units UIPP ps ps ps ps ns ns ps ns ns ns 2Bt2 + tSKTX 2Bt2 + tSKTX 1.5 -- -- 1.0 tHSITXDDATAS TXD Data Setup Time tHSITXDDATAH TXD Data Hold Time 1. The SIN and SOUT jitter specifications listed above are under the condition that the clock tree that drives the REFCLK to sysHSI Block is in sysCLOCK PLL BYPASS mode. 2. Bt = bit time period. High speed serial bit time. 3. Internal timing for reference only. 33 Lattice Semiconductor DESERIALIZER Timing1 Symbol fDSIN eoSIN ber tSKRX tCKISIN tHSIOUTVALIDPRE Description SIN Frequency Deviation from REFCLK SIN Eye Opening Tolerance Bit Error Rate Skew Margin Between SIN and SS_CLKIN SS_CLKIN to bit0 of SIN RXD, LOSS, CDRLOCK, SYDT Valid Time Before RECCLK Falling Edge Mode 8B10B/ 10B12B All CDR SS (Note 1) All SS SS All All All CDR SS ispXPGA Family Data Sheet Conditions Min. -100 0.4 0.65 -- Max. +100 -- -- 10-12 0.125 Units ppm UIPP UIPP Bits UIPP ns ns ns ns ns Note 2 Note 2 Note 3 Note 3 -- 2Bt - tSKRX 2Bt + tSKRX tRCP / 2-0.7 tRCP / 2-0.7 1.5tRCP + 4.5Bt + 2 -- -- 1.5tRCP + 4.5Bt + 10 1.5tRCP + 1.5Bt + 15 tHSIOUTVALIDPOST RXD, LOSS, CDRLOCK, SYDT Valid Time After RECCLK Falling Edge Bit 0 of SIN Delay to RXD Valid at RECCLK Falling edge tDSIN Note 2 1.5tRCP + 1.5Bt + 3 1. ispXPGA only. RX_SS mode only. This limit is increased if EO is increased. 2. SS Normal Receive Mode (no de-skew option). 3. Internal timing for reference only. Lock-in Timing CDRX_SS LOCK-IN (DE-SKEW) TIMING SIN CAL CDRLOCK SYDT RXD(0:7) MIN. 1200 SYNCPAT MIN. 1100 LS CYCLE DATA (SERIAL ) tSUSYNC tCDRLOCK SYNCPAT TRAINING SEQUENCE tHDSYNC DATA (PARALLEL) SS MODE DATA TRANSFER CDR_10B12B LOCK-IN TIMING SIN CDRLOCK SYDT RXD(0:9) 1024 SYNCPAT DATA (SERIAL ) tCDRLOCK SYNCPAT DATA (PARALLEL) 34 Lattice Semiconductor Lock-in Timing (Continued) CDR_8B10B LOCK-IN TIMING SIN CDRLOCK SYDT RXD(0:9) 120 Idle Pattern(480 TRCP) ispXPGA Family Data Sheet DATA (SERIAL ) t CDRLOCK Idle Pattern DATA (PARALLEL) SYDT Timing SYDT TIMING FOR CDRX_10B12B RECCLK SYDT RXD(0:9) SYNC PATTERN Data0 Data1 Data2 Data3 Data4 Parallel Data SYDT TIMING FOR CDRX_8B10B RECCLK SYDT RXD(0:9) K28.5 D21.4 D21.5 D21.5 K28.5 D21.4 D21.5 D21.5 D0 D1 D2 IDLE PATTERN IDLE PATTERN Data Serializer Timing 8B/10B SERIALIZER DELAY TIMING TXD SYMBOL N tCOSOUT SYMBOL N+1 REFCLK SOUT b4 b5 b6 b7 b8 b9 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b0 b1 b2 SYMBOL N-1 SYMBOL N SYMBOL N+1 35 Lattice Semiconductor Serializer Timing (Continued) 10B/12B SERIALIZER DELAY TIMING ispXPGA Family Data Sheet TXD SYMBOL N t COSOUT SYMBOL N+1 REFCLK SOUT b4 b5 b6 b7 b8 b9 "0" "1" b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 "0" "1" SYMBOL N-1 SYMBOL N SS Mode SERIALIZER DELAY TIMING TXD REFCLK t COSOUT SYMBOL N SYMBOL N+1 SS_CLKOUT t CKOSOUT SOUT b4 b5 b6 b7 b0 b1 b2 b3 t SKTX b4 b5 b6 b7 b0 SYMBOL N+1 SYMBOL N-1 SYMBOL N INTERNAL TIMING FOR sysHSI BLOCK REFCLK tHSITXDDATAS t PWREFCLK tHSITXDDATAH TXD Deserializer Timing 8B/10B DESERIALIZER DELAY TIMING SYMBOL N SIN SYMBOL N+1 SYMBOL N+2 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b0 b1 b2 b3 b4 b5 TDSIN RECCLK RXD SYMBOL N-1 SYMBOL N 36 Lattice Semiconductor Deserializer Timing (Continued) 10B/12B DESERIALIZER DELAY TIMING SYMBOL N SIN SYMBOL N+1 ispXPGA Family Data Sheet SYMBOL N+2 "1" b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 "0" "1" b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 "0" "1" b0 b1 b2 b3 b4 TTDSIN RECCLK RXD SYMBOL N-2 SYMBOL N-1 SYMBOL N CDRX_SS DESERIALIZER DELAY TIMING SYMBOL N SIN b0 b1 b2 b3 b4 b5 b6 b7 TDSIN RECCLK RXD SYMBOL N-2 SYMBOL N-1 SYMBOL N b0 b1 SYMBOL N+1 b2 b3 b4 b5 b6 b7 b0 b1 SYMBOL N+2 b2 b3 b4 RX_SS DESERIALIZER DELAY TIMING SS_CLKIN TCKISIN SIN b6 b7 b0 b1 SYMBOL N b2 b3 b4 b5 b6 b7 TDSIN RECCLK RXD SYMBOL N-2 SYMBOL N-1 SYMBOL N b0 b1 SYMBOL N+1 b2 b3 b4 b5 b6 b7 SYMBOL N+2 b0 b1 b2 INTERNAL TIMING FOR sysHSI BLOCK RECCLK t HSIOUTVALIDPRE LOSS, SYDT, RXD, CDRLOCK t HSIOUTVALIDPOST 37 Lattice Semiconductor ispXPGA Family Data Sheet sysCLOCK PLL Timing Over Recommended Operating Conditions Symbol tPWH tPWL tR, tF tINSTB fMDIVIN fMDIVOUT fNDIVIN fNDIVOUT fVDIVIN fVDIVOUT tOUTDUTY Parameter Input clock, high time Input clock, low time Input Clock, rise and fall time Input clock stability, cycle to cycle (peak) M Divider input, frequency range M Divider output, frequency range N Divider input, frequency range N Divider output, frequency range V Divider input, frequency range V Divider output, frequency range output clock, duty cycle Clean reference. 10 MHz < fMDIVOUT < 20 MHz or 100MHz < fVDIVIN < 160 MHz Clean reference. 20 MHz < fMDIVOUT < 320 MHz and 160MHz < fVDIVIN < 320 MHz Clean reference. 10 MHz < fMDIVOUT < 20 MHz or 100MHz < fVDIVIN < 160 MHz Clean reference. 20 MHz < fMDIVOUT < 320 MHz and 160MHz < fVDIVIN < 320 MHz Internal feedback External feedback Typical = +/- 250ps Conditions 80% to 80% 20% to 20% 20% to 80% Min 1.2 1.2 -- -- 10 10 10 10 100 10 40 -- Max -- -- 3.0 +/- 250 320 320 320 320 400 320 60 +/- 250 Units ns ns ns ps MHz MHz MHz MHz MHz MHz % ps tJIT(CC) Output clock, cycle to cycle jitter (peak) -- +/- 150 ps -- +/- 300 ps TJIT(PERIOD) Output clock, period jitter (peak) -- -- -- -- +/- 150 3.0 600 25 ps ns ps us ps ns ns ns ns tCLK_OUT_DELAY Input clock to CLK_OUT delay tPHASE tLOCK tPLL_DELAY tRANGE tPLL_RSTW tCLK_IN3 Input clock to external feedback delta Time to acquire phase lock after input stable Delay increment (Lead/Lag) Total output delay range (lead/lag) Minimum reset pulse width Global clock input delay +/- 120 +/- 550 +/- 0.84 +/- 3.85 -- -- -- 1.8 1.0 1.5 tPLL_SEC_DELAY Secondary PLL output delay (tPLL_DELAY) 1. This condition assures that the output phase jitter will remain within specification 2. Accumulated jitter measured over 10,000 waveform samples 3. Internal timing for reference only. 38 Lattice Semiconductor ispXPGA Family Data Sheet ispXP sysCONFIG Port Timing Specifications Symbol sysCONFIG Write Cycle Timing tSUCS tHCS tSUWD tHWD tPRGM tWINIT tIODISS tWRDY tIOENSS tWH tWL fMAXW tHREAD tSUREAD tRH tRL fMAXR tCORD Input setup time of CS to CCLK rise Hold time of CS to CCLK Rise Input setup time of write data to CCLK rise Hold time of write data to CCLK rise Low time to reset device SRAM INIT pulse width User I/O disable Time to write data into SRAM User I/O enable Write clock High pulse width Write clock Low pulse width Write fMAX Hold time of READ to CCLK rise Input setup time of READ High to CCLK rise READ clock high pulse width READ clock low pulse width Read fMAX Clock to out for read data 12 0 12 0 5 4 -- -- -- 12 12 -- 0 30 12 15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50 -- 30 4 30 -- -- 25 -- -- -- -- 25 25 ns ns ns ns ns ms ns ms ns ns ns MHz ns ns ns ns MHz ns Timing Parameter Min. Typ. Max. Units sysCONFIG Read Cycle Timing Boundary Scan Timing Parameter tBTCP tBTCPH tBTCPL tBTS tBTH tBTRF tBTCO tBTCODIS tBTCOEN tBTCRS tBTCRH tBUTCO tBTUODIS tBTUPOEN Description TCK [BSCAN] Clock Pulse Width TCK [BSCAN] Clock Pulse Width High TCK [BSCAN] Clock Pulse Width Low TCK [BSCAN] Setup Time TCK [BSCAN] Hold Time TCK [BSCAN] Rise/Fall Time TAP Controller Falling Edge of Clock to Valid Output TAP Controller Falling Edge of Clock to Valid Disable TAP Controller Falling Edge of Clock to Valid Enable BSCAN Test Capture Register Setup Time BSCAN Test Capture Register Hold Time BSCAN Test Update Register, Falling Edge of Clock to Valid Output BSCAN Test Update Register, Falling Edge of Clock to Valid Disable BSCAN Test Update Register, Falling Edge of Clock to Valid Enable Min. 40 20 20 8 10 50 -- -- -- 8 25 -- -- -- Max. -- -- -- -- -- -- 18 18 18 -- -- 45 20 20 Units ns ns ns ns ns mV/ns ns ns ns ns ns ns ns ns 39 Lattice Semiconductor ispXPGA Family Data Sheet Switching Test Conditions Figure 24 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 8. Figure 24. Output Test Load, LVTTL and LVCMOS Standards VCCO R1 Device Output R2 CL* Test Point *CL includes test fixture and probe capacitance. Table 8. Text Fixture Required Components Test Condition LVCMOS I/O, (L -> H, H -> L) Default LVCMOS 1.8 I/O (Z -> H) Default LVCMOS 1.8 I/O (Z -> L) Default LVCMOS 1.8 I/O (H -> Z) Default LVCMOS 1.8 I/O (L -> Z) R1 106 106 106 R2 106 106 106 CL 35pF 35pF 35pF 5pF 5pF Timing Reference LVCMOS 3.3 = VCCO/2 LVCMOS 2.5 = VCCO/2 LVCMOS 1.8 = VCCO/2 0.9V 0.9V VOH - 0.3 VOL + 0.3 VCCO LVCMOS 3.3 = 3.0V LVCMOS 2.5 = 2.3V LVCMOS 1.8 = 1.65V 1.65V 1.65V 1.65V 1.65V Note: Output test conditions for all other interfaces are determined by the respective standards. 40 Lattice Semiconductor ispXPGA Family Data Sheet Signal Descriptions1 Signal Name General Purpose BKy_IOx1,2 GCLKn/In 7 GSR NC GND VCC VCCJ VCCOy2 VREFy 2 Signal Type Input/Output Input Input -- GND VCC VCC VCC Input Output Description General purpose I/O number x in I/O Bank y Global clock/input8 Global Set/Reset No Connect Ground Core logic power supply IEEE 1149.1 TAP power supply I/O Bank y power supply I/O Bank y reference voltage Temperature Sensing Diodes, provide a differential voltage, which corresponds to the temperature of the device. Test Mode Select Test Clock Test Data In Test Data Out Test Output Enable tri-states all I/O pins Selects the SRAM memory configuration type (Peripheral or E2CMOS Refresh) Initiates download from E2CMOS or the peripheral port to SRAM memory (active low) DXN, DXP Test and Program/Configuration TMS TCK TDI TDO TOE CFG0 PROGRAMb DONE INITb READ CCLK CSb DATA[0:7] sysCLOCK PLL3 PLL_FBKz PLL_RSTz CLK_OUTz PLL_LOCKz GNDP VCCP sysHSI Block4, 5 HSImA_SINP, HSImB_SINP HSImA_SINN, HSImB_SINN HSImA_SOUTP, HSImB_SOUTP HSImA_SOUTN, HSImB_SOUTN HSImA_LOSS, HSImB_LOSS HSImA_SYDT, HSImB_SYDT HSImA_RECCLK, HSImB_RECCLK HSImA_CDRLOCK, HSImB_CDRLOCK Input Input Input Output Input Input Input Bi-directional Indicates when configuration is complete Bi-directional Indicates the device is ready for programming (active low) Input Input Input Selects the READ operation when in sysCONFIG mode sysCONFIG Configuration Clock sysCONFIG Chip Select (active low) Bi-directional sysCONFIG Peripheral Port Data I/O Input Input Optional external feedback Optional external M divider reset Internal Signal Clock output (routable to any I/O) Internal Signal Lock output (routable to any I/O) GND VCC Input Input Output Output PLL Ground PLL power supply P-side of differential serial data input N-side of differential serial data input P-side of differential serial data output N-side of differential serial data output Internal Signal Detects loss of signal Internal Signal Symbol alignment detect Internal Signal Recovered clock Internal Signal Indicates when the CDR circuit is locked 41 Lattice Semiconductor ispXPGA Family Data Sheet Signal Descriptions1 (Continued) Signal Name HSImA_CDRRST, HSImB_CDRRST HSImA_EXLOSS, HSImB_EXLOSS HSIm_CSLOCK, HSIm_CSLOCK SS_CLKIN0P, SS_CLKIN1P SS_CLKIN0N, SS_CLKIN1N SS_CLKOUT0P, SS_CLKOUT1P SS_CLKOUT0N, SS_CLKOUT1N CAL0, CAL1 1. 2. 3. 4. 5. 6. 7. 8. Signal Type Input Input CDR Reset Description External loss indicates data on SIN is invalid, forces LOSS to "1" Internal Signal Indicates when the CSPLL circuit is locked Input Input Output Output Input P-side of differential clock input N-side of differential clock input P-side of differential clock output N-side of differential clock output Initiates source synchronous calibration sequence sysHSI Block (Source Synchronous Mode)6 x is a variable for the I/O number. y is a variable for the I/O Bank. z is a variable for the PLL number. m is a variable for the sysHSI block number. A and B refer to the sysHSI block channels. 0 and 1 refer to Source Synchronous group 0 and 1 n is a variable for the GCLK and Input number See Logic Signal Connections Table for differential pairing. 42 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Power Supply and NC Connections1 Signal VCC 256-Ball fpBGA3 516-Ball fpBGA3 C3, C14, D4, D13, E5, E12, F6, F11, A9, A22, D4, D27, J1, J30, L11, L12, L15, L16, L19, L20, M11, M20, R11, L6, L11, M5, M12, N4, N13, P3, P14 R20, T11, T20, W11, W20, Y11, Y12, Y15, Y16, Y19, Y20, AB1, AB30, AG4, AG27, AK9, AK22 F5, G5 K5, L5 M6, M7 M10, M11 K12, L12 G12, F12 E10, E11 E6, E7 H3, J15 A2 A1, A16, B2, B15, F7, F8, F9, F10, G6, G7, G8, G9, G10, G11, H6, H7, H8, H9, H10, H11, J6, J7, J8, J9, J10, J11, K6, K7, K8, K9, K10, K11, L7, L8, L9, L10, R2, R15, T1, T16 H15, J4 -- F4, J4, M4, N11, P4, P11 U4, U11, V11, W4, AB4, AE4 Y13, Y14, AG6, AG9, AG12, AG14 Y17, Y18, AG17, AG19, AG22, AG25 U20, U27, V20, W27, AB27, AE27 F27, J27, M27, N20, P20, P27 D17, D19, D22, D25, L17, L18 D6, D9, D12, D14, L13, L14 R4, T30 C4 A1, A30, B2, B29, C3, C28, M12, M13, M14, M15, M16, M17, M18, M19, N12, N13, N14, N15, N16, N17, N18, N19, P12, P13, P14, P15, P16, P17, P18, P19, R12, R13, R14, R15, R16, R17, R18, R19, T12, T13, T14, T15, T16, T17, T18, T19, U12, U13, U14, U15, U16, U17, U18, U19, V12, V13, V14, V15, V16, V17, V18, V19, W12, W13, W14, W15, W16, W17, W18, W19, AH3, AH28, AJ2, AJ29, AK1, AK30 R29, T4 LFX125: A10, A13, A16, A17, A24, A25, A26, A4, A5, A6, A7, AA1, AA2, AA28, AA29, AA3, AB28, AC1, AC28, AD1, AD27, AD4, AE28, AE29, AE3, AE30, AF27, AF28, AF29, AF3, AF4, AG1, AG10, AG11, AG15, AG2, AG20, AG23, AG24, AG29, AG3, AG8, AH1, AH15, AH19, AH2, AH20, AH23, AH24, AH30, AH7, AH8, AH9, AJ1, AJ12, AJ14, AJ15, AJ19, AJ20, AJ21, AJ23, AJ24, AJ25, AJ27, AJ30, AJ6, AJ7, AJ8, AK11, AK14, AK15, AK20, AK21, AK23, AK24, AK25, AK27, AK5, AK6, AK7, B10, B13, B16, B17, B18, B23, B24, B25, B5, B6, B7, C11, C13, C14, C16, C17, C22, C23, C24, C25, C6, C7, C8, D11, D16, D23, D24, D28, D29, D3, D7, D8, E30, E4, F1, F29, F30, G1, G2, G27, G28, G29, G30, H1, H2, H27, H28, H29, H30, J2, J28, J29, J3, K1, K2, K27, K28, K3, K4, L1, L2, L27, L3, L4, M1, M2, M29, M3, M30, V27, V28, V3, V4, W1, W30, Y1, Y27, Y28, Y3, Y30 LFX200: A26, A25, A24, A17, A10, A7, A6, A5, A4, B25, B24, B23, B17, B10, B7, B6, B5, C25, C24, C23, C22, C16, C11, C8, C7, C6, D24, D23, D16, D11, D8, D7, E30, F30, F29, F1, G30, G29, G28, G27, G2, G1, H30, H29, H28, H27, H2, H1, J29, J28, J3, J2, K28, K27, K4, K3, K2, K1, L27, L4, L3, L2, L1, M3, V28, V27, V4, V3, W30, W1, Y30, Y28, Y27, Y3, Y1, AA29, AA28, AA3, AA2, AA1, AD27, AD4, AE28, AE3, AF29, AF28, AF27, AF3, AG29, AG24, AG23, AG20, AG11, AG10, AG8, AG2, AG1, AH30, AH24, AH23, AH20, AH9, AH8, AH7, AH2, AH1, AJ30, AJ27, AJ25, AJ24, AJ23, AJ21, AJ15, AJ12, AJ8, AJ7, AJ6, AJ1, AK27, AK25, AK24, AK23, AK21, AK15, AK11, AK7, AK6, AK5 1. All grounds must be electrically connected at the board level. 2. NC pins should not be connected to any active signals, VCC or GND. 3. Balls for GND, VCC and VCCOx are connected within the substrate to their respective common signals. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally. VCCO0 VCCO1 VCCO2 VCCO3 VCCO4 VCCO5 VCCO6 VCCO7 VCCP VCCJ GND GNDP NC2 43 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Power Supply and NC Connections1 (Continued) Signal VCC 680-Ball fpBGA3 900-Ball fpBGA3 AE35, AE5, AL5, AR15, AR25, AR31, AR35, AR5, L11, L20, M12, M13, M14, M17, M18, M19, N12, N19, P12, P19, AT36, AT4, AU3, AU37, C3, C37, D36, D4, E15, E25, U12, U19, V12, V19, W12, W13, W14, W17, W18, W19, Y11, Y20 E35, E5, E9, J35, R35, R5 E11, E12, E13, E17, E18, E7 E22, E23, E27, E29, E31, E33 G35, L35, M35, N35, U35, V35 AB35, AC35, AG35, AJ35, AL35, AN35 AR22, AR23, AR27, AR28, AR29, AR33 AR11, AR13, AR17, AR18, AR7, AR9 AB5, AC5, AG5, AH5, AJ5, AN5 G5, J5, L5, N5, U5, V5 E20, AW22 D3 A1, A2, A20, A38, A39, AE3, AE37, AK3, AK37, AR36, AR4, AT20, AT35, AT5, AU10, AU14, AU20, AU26, AU30, AV1, AV2, AV20, AV38, AV39, AW1, AW2, AW20, AW38, AW39, B1, B2, B20, B38, B39, C10, C14, C20, C26, C30, D20, D35, D5, E36, E4, K3, K37, P37, R3, Y1, Y2, Y3, Y36, Y37, Y38, Y39, Y4 AR20, A21 A3, B29, AW3, AV3, AW11, AV11, AV29, AW29, AW37, B3, AV37, C39, C38, AU39, AU38, AJ39, AJ38, N38, N39, C2, C1, AU1, AU2, AJ2, AJ1, N2, N1, B11, A11, A37, B37, A29 K3, L10, M11, N11, N5, P11, R11, R12 AA3, T11, T12, U11, V11, V5, W11, Y10 AA11, AF13, AH10, W15, Y12, Y13, Y14, Y15 AA20, AF18, AH21, W16, Y16, Y17, Y18, Y19 AA28, T19, T20, U20, V20, V26, W20, Y21 K28, L21, M20, N20, N26, P20, R19, R20 C21, E18, K20, L16, L17, L18, L19, M16 C10, E13, K11, L12, L13, L14, L15, M15 R5, T26 B3 A1, A2, A29, A30, AB28, AB3, AG27, AG4, AH22, AH28, AH3, AH9, AJ1, AJ2, AJ29, AJ30, AK1, AK2, AK29, AK30, B1, B2, B29, B30, C22, C28, C3, C9, D27, D4, J28, J3, N13, N14, N15, N16, N17, N18, P13, P14, P15, P16, P17, P18, R13, R14, R15, R16, R17, R18, T13, T14, T15, T16, T17, T18, U13, U14, U15, U16, U17, U18, V13, V14, V15, V16, V17, V18 R28, T3 LFX500: A8, A9, A10, A11, A19, A20, A21, A22, B8, B9, B10, B11, B19, B20, B21, B22, C1, C2, C11, C12, C19, C20, C23, D3, D10, D11, D12, D19, D20, D21, D22, D23, E3, E10, E11, E12, E21, E22, E28, E29, E30, F1, F2, F10, F11, F12, F21, F26, F29, F30, G1, G2, G3, G4, G10, G25, G26, G27, G28, G29, G30, H1, H2, H3, H4, H27, H28, H29, H30, J1, J2, J4, J5, J6, J7, J24, J25, J26, J27, W25, W26, Y3, Y4, Y5, Y6, Y25, Y26, Y27, Y28, AA4, AA5, AA16, AA17, AA18, AA19, AA21, AA26, AA27, AB1, AB2, AB4, AB5, AB6, AB7, AB24, AB25, AB26, AB27, AC1, AC2, AC3, AC4, AC5, AC6, AC27, AC28, AC29, AC30, AD1, AD2, AD10, AD21, AD29, AD30, AE10, AE11, AE12, AE19, AE20, AE21, AE29, AE30, AF10, AF11, AF12, AF19, AF20, AF21, AF22, AG10, AG11, AG12, AG19, AG20, AG21, AG22, AH11, AH12, AH19, AH20, AJ8, AJ9, AJ10, AJ11, AJ20, AJ21, AJ22, AK8, AK9, AK10, AK11, AK20, AK21, AK22 LFX1200: AA22, AA23, AA24, AA25, AB23, AC24, T21, T22, T23, T24, T25, U21, U22, U23, U24, V21, V22, V23, W21, W22, W23, W24, Y22, Y23, Y24, AA16, AA17, AA18, AA19, AA21, AB16, AB17, AB18, AB19, AB20, AB21, AB22, AC16, AC17, AC18, AC19, AC20, AC21, AC22, AC23, AD16, AD17, AD19, AD20, AD22, AD23, AD24, AE22, AE25, AF25, AF26, AA10, AA12, AA13, AA14, AA15, AB10, AB11, AB12, AB13, AB14, AB15, AB9, AC10, AC11, AC12, AC13, AC14, AC15, AC8, AC9, AD11, AD12, AD14, AD15, AD7, AD8, AD9, AE6, AE9, AF5, AF6, H24, J23, K22, K23, K24, K25, L22, L23, L24, M21, M22, M23, M24, N21, N22, N23, P21, P22, P23, P24, R21, R22, R23, R24, R25, AA6, AA7, AA8, AA9, AB8, AC7, T10, T6, T7, T8, T9, U10, U7, U8, U9, V10, V8, V9, W10, W7, W8, W9, Y7, Y8, Y9, H5, H6, H7, J8, K6, K7, K8, K9, L7, L8, L9, M10, M7, M8, M9, N10, N8, N9, P10, P7, P8, P9, R10, R8, R9, E25, E26, F22, F25, G16, G17, G19, G20, G22, G23, G24, H16, H17, H18, H19, H20, H21, H22, H23, J16, J17, J18, J19, J20, J21, J22, K16, K17, K18, K19, K21, E5, E6, F6, F9, G11, G12, G14, G15, G7, G8, G9, H10, H11, H12, H13, H14, H15, H8, H9, J10, J11, J12, J13, J14, J15, J9, K10, K12, K13, K14, K15 VCCO0 VCCO1 VCCO2 VCCO3 VCCO4 VCCO5 VCCO6 VCCO7 VCCP VCCJ GND GNDP NC2 1. All grounds must be electrically connected at the board level. 2. NC pins should not be connected to any active signals, VCC or GND. 3. Balls for GND, VCC and VCCOx are connected within the substrate to their respective common signals. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally. 44 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 256-Ball fpBGA LFX200 256-fpBGA Ball C2 D2 B1 C1 D3 E3 D1 E1 E2 F2 F1 G1 F3 G2 E4 F4 H1 J1 H2 G3 G4 H4 H3 J4 J2 J3 H5 J5 K1 L1 K4 L4 K3 Signal Name BK0_IO2 GND (Bank 0) BK0_IO3 BK0_IO6 BK0_IO7 BK0_IO8 BK0_IO9 BK0_IO10 GND (Bank 0) BK0_IO11 BK0_IO12 BK0_IO13 BK0_IO14 BK0_IO15 BK0_IO18 GND (Bank 0) BK0_IO19 BK0_IO20 BK0_IO21 BK0_IO22 BK0_IO23 BK0_IO24 BK0_IO25 GND (Bank 0) GCLK0 GCLK1 VCCP0 GNDP0 GCLK2 GCLK3 GND (Bank 1) BK1_IO0 BK1_IO1 BK1_IO2 BK1_IO3 BK1_IO4 BK1_IO5 BK1_IO6 Second Function HSI0A_SOUTP HSI0A_SOUTN HSI0A_SINP HSI0A_SINN VREF0 HSI0B_SOUTP HSI0B_SOUTN HSI0B_SINP HSI0B_SINN PLL_FBK0 PLL_RST1 PLL_FBK1 PLL_RST0 CLK_OUT0 CLK_OUT1 CLK_OUT2 CLK_OUT3 SS_CLKOUT0P SS_CLKOUT0N PLL_FBK2 PLL_FBK3 SS_CLKIN0P LVDS Pair/ Polarity 1P 1N 3P 3N 4P 4N 5P 5N 6P 6N 7P 7N 9P 9N 10P 10N 11P 11N 12P 12N LVDSCLK0 LVDSCLK0 LVDSCLK1 LVDSCLK1 13P 13N 14P 14N 15P 15N 16P Signal Name BK0_IO0 BK0_IO1 BK0_IO4 GND (Bank 0) BK0_IO5 BK0_IO6 BK0_IO7 BK0_IO8 BK0_IO9 BK0_IO10 BK0_IO11 BK0_IO12 GND (Bank 0) BK0_IO13 BK0_IO14 BK0_IO15 BK0_IO16 BK0_IO17 BK0_IO18 GND (Bank 0) BK0_IO19 BK0_IO20 BK0_IO21 GCLK0 GCLK1 VCCP0 GNDP0 GCLK2 GCLK3 BK1_IO0 BK1_IO1 BK1_IO2 GND (Bank 1) BK1_IO3 BK1_IO4 BK1_IO5 BK1_IO6 LFX125 Second Function HSI0A_SOUTP HSI0A_SOUTN HSI0A_SINP HSI0A_SINN VREF0 HSI0B_SOUTP HSI0B_SOUTN HSI0B_SINP HSI0B_SINN PLL_FBK0 PLL_RST1 PLL_FBK1 PLL_RST0 CLK_OUT0 CLK_OUT1 CLK_OUT2 CLK_OUT3 SS_CLKOUT0P SS_CLKOUT0N PLL_FBK2 PLL_FBK3 SS_CLKIN0P LVDS Pair/ Polarity 0P 0N 2P 2N 3P 3N 4P 4N 5P 5N 6P 6N 7P 7N 8P 8N 9P 9N 10P 10N LVDSCLK0 LVDSCLK0 LVDSCLK1 LVDSCLK1 11P 11N 12P 12N 13P 13N 14P 45 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 256-Ball fpBGA (Continued) LFX200 256-fpBGA Ball L3 K2 L2 M1 N1 M3 M4 M2 P1 R1 N3 N2 P2 P4 T2 T3 R3 R4 N5 P5 T4 T5 N6 P6 R5 R6 N7 P7 T6 T7 M8 M9 R7 Signal Name GND (Bank 1) BK1_IO7 BK1_IO8 BK1_IO9 BK1_IO10 BK1_IO11 BK1_IO12 BK1_IO13 GND (Bank 1) BK1_IO161 BK1_IO18 BK1_IO19 BK1_IO201 BK1_IO22 GND (Bank 1) BK1_IO23 TCK TMS TOE BK2_IO0 BK2_IO1 BK2_IO2 GND (Bank 2) BK2_IO3 BK2_IO6 BK2_IO7 BK2_IO8 BK2_IO9 BK2_IO10 GND (Bank 2) BK2_IO11 BK2_IO12 BK2_IO13 BK2_IO14 BK2_IO15 BK2_IO16 BK2_IO17 BK2_IO18 Second Function SS_CLKIN0N HSI1A_SOUTP HSI1A_SOUTN PLL_RST2 PLL_RST3 VREF1 HSI1B_SOUTP HSI1B_SOUTN HSI1B_SINP HSI1B_SINN VREF2 LVDS Pair/ Polarity 16N 17P 17N 18P 18N 19P 19N 22P 22N 24P 24N 26P 26N 27P 27N 29P 29N 30P 30N 31P 31N 32P 32N 33P 33N 34P 34N 35P Signal Name BK1_IO7 BK1_IO8 GND (Bank 1) BK1_IO9 BK1_IO10 BK1_IO11 BK1_IO12 BK1_IO13 BK1_IO141 BK1_IO16 GND (Bank 1) BK1_IO17 BK1_IO181 BK1_IO20 BK1_IO21 TCK TMS TOE BK2_IO0 BK2_IO1 BK2_IO2 BK2_IO3 GND (Bank 2) BK2_IO6 BK2_IO7 BK2_IO8 BK2_IO9 BK2_IO10 BK2_IO11 BK2_IO12 GND (Bank 2) BK2_IO13 BK2_IO14 BK2_IO15 BK2_IO16 BK2_IO17 BK2_IO18 LFX125 Second Function SS_CLKIN0N PLL_RST2 PLL_RST3 VREF1 VREF2 LVDS Pair/ Polarity 14N 15P 15N 16P 16N 17P 17N 19P 19N 21P 21N 22P 22N 23P 23N 25P 25N 26P 26N 27P 27N 28P 28N 29P 29N 30P 30N 31P 46 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 256-Ball fpBGA (Continued) LFX200 256-fpBGA Ball R8 N8 P8 T8 T9 R9 R10 P9 N9 T10 T11 P10 N10 R11 R12 P11 N11 T12 T13 R13 R14 P12 N12 T14 T15 P13 P15 N14 R16 P16 N15 Signal Name GND (Bank 2) BK2_IO19 BK2_IO20 BK2_IO21 GND (Bank 2) GND (Bank 3) BK3_IO0 BK3_IO1 BK3_IO2 BK3_IO3 BK3_IO4 BK3_IO5 BK3_IO6 GND (Bank 3) BK3_IO7 BK3_IO8 BK3_IO9 BK3_IO14 GND (Bank 3) BK3_IO15 BK3_IO16 BK3_IO17 BK3_IO18 BK3_IO19 BK3_IO20 BK3_IO21 BK3_IO22 GND (Bank 3) BK3_IO23 RESET DXP DXN BK4_IO0 BK4_IO1 BK4_IO2 GND (Bank 4) BK4_IO3 BK4_IO4 Second Function VREF3 HSI2A_SINP HSI2A_SINN LVDS Pair/ Polarity 35N 36P 36N 39P 39N 40P 40N 41P 41N 42P 42N 43P 43N 46P 46N 47P 47N 48P 48N 49P 49N 50P 50N 52P 52N 53P 53N 54P Signal Name GND (Bank 2) BK2_IO19 BK2_IO20 BK2_IO21 BK3_IO0 BK3_IO1 BK3_IO2 GND (Bank 3) BK3_IO3 BK3_IO4 BK3_IO5 BK3_IO6 BK3_IO7 BK3_IO8 GND (Bank 3) BK3_IO9 BK3_IO10 BK3_IO11 BK3_IO12 BK3_IO13 BK3_IO14 BK3_IO15 BK3_IO16 GND (Bank 3) BK3_IO17 BK3_IO18 BK3_IO19 RESET DXP DXN BK4_IO0 BK4_IO1 BK4_IO2 BK4_IO3 BK4_IO4 GND (Bank 4) LFX125 Second Function VREF3 LVDS Pair/ Polarity 31N 32P 32N 33P 33N 34P 34N 35P 35N 36P 36N 37P 37N 38P 38N 39P 39N 40P 40N 41P 41N 42P 42N 44P 44N 45P 45N 46P - 47 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 256-Ball fpBGA (Continued) LFX200 256-fpBGA Ball M15 M14 M13 L13 L14 N16 M16 L15 K15 K14 K13 L16 K16 J13 J12 J14 H14 J15 H15 J16 H16 H12 H13 G14 G15 G13 F13 G16 F16 F14 F15 E16 Signal Name BK4_IO5 BK4_IO8 BK4_IO9 GND (Bank 4) BK4_IO12 BK4_IO13 BK4_IO14 BK4_IO15 BK4_IO18 GND (Bank 4) BK4_IO19 BK4_IO20 BK4_IO21 BK4_IO22 BK4_IO23 BK4_IO24 BK4_IO25 GND (Bank 4) GCLK4 GCLK5 VCCP1 GNDP1 GCLK6 GCLK7 GND (Bank 5) BK5_IO0 BK5_IO1 BK5_IO2 BK5_IO3 BK5_IO6 GND (Bank 5) BK5_IO7 BK5_IO10 BK5_IO11 BK5_IO12 BK5_IO13 BK5_IO14 GND (Bank 5) Second Function VREF4 PLL_RST4 PLL_RST5 HSI2B_SOUTP HSI2B_SOUTN SS_CLKIN1P SS_CLKIN1N PLL_FBK4 PLL_FBK5 SS_CLKOUT1P SS_CLKOUT1N CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 PLL_RST7 PLL_RST6 HSI3A_SINP HSI3A_SINN HSI3A_SOUTP LVDS Pair/ Polarity 54N 56P 56N 58P 58N 59P 59N 61P 61N 62P 62N 63P 63N 64P 64N LVDSCLK2 LVDSCLK2 LVDSCLK3 LVDSCLK3 65P 65N 66P 66N 68P 70P 70N 71P 71N 72P Signal Name BK4_IO5 BK4_IO6 BK4_IO7 BK4_IO8 BK4_IO9 BK4_IO10 BK4_IO11 GND (Bank 4) BK4_IO14 BK4_IO15 BK4_IO16 BK4_IO17 BK4_IO18 GND (Bank 4) BK4_IO19 BK4_IO20 BK4_IO21 GCLK4 GCLK5 VCCP1 GNDP1 GCLK6 GCLK7 BK5_IO0 BK5_IO1 BK5_IO2 GND (Bank 5) BK5_IO3 BK5_IO6 BK5_IO7 BK5_IO8 GND (Bank 5) BK5_IO9 BK5_IO10 BK5_IO11 BK5_IO12 LFX125 Second Function VREF4 PLL_RST4 PLL_RST5 SS_CLKIN1P SS_CLKIN1N PLL_FBK4 PLL_FBK5 SS_CLKOUT1P SS_CLKOUT1N CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 PLL_RST7 PLL_RST6 PLL_FBK7 HSI1A_SINP HSI1A-SINN HSI1A_OUTP LVDS Pair/ Polarity 46N 47P 47N 48P 48N 49P 49N 51P 51N 52P 52N 53P 53N 54P 54N LVDSCLK2 LVDSCLK2 LVDSCLK3 LVDSCLK3 55P 55N 56P 56N 58P 58N 59P 59N 60P 60N 61P - 48 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 256-Ball fpBGA (Continued) LFX200 256-fpBGA Ball D16 E13 E14 E15 D15 C16 B16 D14 C15 C13 A15 A14 D12 C12 B14 B13 A13 A12 D11 C11 B12 B11 D10 C10 A11 A10 D9 C9 B10 B9 E9 E8 D8 Signal Name BK5_IO15 BK5_IO16 BK5_IO17 BK5_IO18 BK5_IO19 BK5_IO22 GND (Bank 5) BK5_IO23 BK5_IO24 BK5_IO25 CFG0 DONE PROGRAMb BK6_IO0 BK6_IO1 BK6_IO2 GND (Bank 6) BK6_IO3 BK6_IO4 BK6_IO5 BK6_IO6 BK6_IO7 BK6_IO8 BK6_IO9 BK6_IO10 GND (Bank 6) BK6_IO11 BK6_IO14 BK6_IO15 BK6_IO16 BK6_IO17 BK6_IO18 GND (Bank 6) BK6_IO19 BK6_IO20 BK6_IO21 GND (Bank 6) GND (Bank 7) BK7_IO0 Second Function HSI3A_SOUTN VREF5 HSI3B_SINP HSI3B_SINN HSI3B_SOUTP HSI3B_SOUTN INITb CCLK CSb Read DATA7 DATA6 VREF6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 LVDS Pair/ Polarity 72N 73P 73N 74P 74N 76P 76N 77P 77N 78P 78N 79P 79N 80P 80N 81P 81N 82P 82N 83P 83N 85P 85N 86P 86N 87P 87N 88P 88N 91P Signal Name BK5_IO13 BK5_IO14 BK5_IO15 BK5_IO16 GND (Bank 5) BK5_IO17 BK5_IO20 BK5_IO21 BK5_IO18 BK5_IO19 CFG0 DONE PROGRAMb BK6_IO0 BK6_IO1 BK6_IO2 BK6_IO3 BK6_IO4 GND (Bank 6) BK6_IO5 BK6_IO6 BK6_IO7 BK6_IO8 BK6_IO9 BK6_IO10 BK6_IO11 GND (Bank 6) BK6_IO14 BK6_IO15 BK6_IO16 BK6_IO17 BK6_IO18 GND (Bank 6) BK6_IO19 BK6_IO20 BK6_IO21 BK7_IO0 LFX125 Second Function HSI1A_OUTN VREF5 HSI1B_SINP HSI1B_SINN HSI1B_OUTP HSI1B_OUTN INITb CCLK CSb READ DATA7 DATA6 VREF6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 LVDS Pair/ Polarity 61N 62P 62N 63P 63N 65P 65N 64P 64N 66P 66N 67P 67N 68P 68N 69P 69N 70P 70N 71P 71N 73P 73N 74P 74N 75P 75N 76P 76N 77P 49 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 256-Ball fpBGA (Continued) LFX200 256-fpBGA Ball C8 B8 B7 A9 A8 C7 D7 D6 C6 B6 B5 A7 A6 D5 C5 A5 A4 B4 B3 A3 A2 C4 Signal Name BK7_IO1 BK7_IO2 BK7_IO3 BK7_IO6 GND (Bank 7) BK7_IO7 BK7_IO10 BK7_IO11 BK7_IO12 BK7_IO13 BK7_IO14 GND (Bank 7) BK7_IO15 BK7_IO16 BK7_IO17 BK7_IO18 BK7_IO19 BK7_IO20 BK7_IO21 BK7_IO22 GND (Bank 7) BK7_IO23 TDO VCCJ TDI Second Function VREF7 LVDS Pair/ Polarity 91N 92P 92N 94P 94N 96P 96N 97P 97N 98P 98N 99P 99N 100P 100N 101P 101N 102P 102N Signal Name BK7_IO1 BK7_IO2 BK7_IO3 BK7_IO4 BK7_IO5 BK7_IO6 BK7_IO7 BK7_IO8 GND (Bank 7) BK7_IO9 BK7_IO10 BK7_IO11 BK7_IO12 BK7_IO13 BK7_IO14 BK7_IO15 BK7_IO16 GND (Bank 7) BK7_IO17 BK7_IO18 BK7_IO19 TDO VCCJ TDI LFX125 Second Function VREF7 LVDS Pair/ Polarity 77N 78P 78N 79P 79N 80P 80N 81P 81N 82P 82N 83P 83N 84P 84N 85P 85N 86P 86N - 1. Not available for differential pairs. 50 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 516-Ball fpBGA LFX500 516-Ball BGA Ball E4 D3 E3 F3 C2 B1 G4 G3 C1 D2 H4 H3 D1 E1 E2 F2 G2 F1 J3 K3 K4 L4 H2 J2 G1 H1 L3 M3 K2 L2 K1 L1 M2 M1 N3 N4 N2 N1 P1 R1 P3 P2 LFX200 LVDS Pair/ Polarity 0P 0N 1P 1N 2P 2N 3P 3N 4P 4N 5P 5N 6P 6N 7P 7N 8P 8N 9P 9N 10P 10N 11P 11N 12P 12N 13P 13N 14P 14N 15P 15N 16P 16N 17P 17N 18P 18N 19P 19N 20P 20N LFX125 LVDS Pair/ Polarity 0P 0N 1P 1N 2P 2N 3P 3N 4P 4N 5P 5N 6P Signal Name BK0_IO0 BK0_IO1 BK0_IO2 GND (Bank 0) BK0_IO3 BK0_IO4 BK0_IO5 BK0_IO6 BK0_IO7 BK0_IO8 BK0_IO9 BK0_IO10 GND (Bank 0) BK0_IO11 BK0_IO12 BK0_IO13 BK0_IO14 BK0_IO15 BK0_IO16 BK0_IO17 BK0_IO18 GND (Bank 0) BK0_IO19 BK0_IO20 BK0_IO21 BK0_IO22 BK0_IO23 BK0_IO24 BK0_IO25 BK0_IO26 GND (Bank 0) BK0_IO27 BK0_IO28 BK0_IO29 BK0_IO30 BK0_IO31 BK0_IO32 BK0_IO33 BK0_IO34 GND (Bank 0) BK0_IO35 BK0_IO36 BK0_IO37 BK0_IO38 BK0_IO39 BK0_IO40 GND (Bank 0) BK0_IO41 Second Function HSI0A_SOUTP HSI0A_SOUTN HSI0A_SINP HSI0A_SINN VREF0 HSI0B_SOUTP HSI0B_SOUTN HSI0B_SINP HSI0B_SINN HSI1A_SOUTP HSI1A_SOUTN HSI1A_SINP HSI1A_SINN HSI1B_SOUTP HSI1B_SOUTN HSI1B_SINP HSI1B_SINN PLL_FBK0 PLL_RST1 PLL_FBK1 PLL_RST0 CLK_OUT0 CLK_OUT1 Signal Name BK0_IO0 BK0_IO1 BK0_IO2 GND (Bank 0) BK0_IO3 BK0_IO4 BK0_IO5 BK0_IO6 BK0_IO7 BK0_IO8 BK0_IO9 BK0_IO10 GND (Bank 0) BK0_IO11 BK0_IO12 BK0_IO13 BK0_IO14 BK0_IO15 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC BK0_IO16 BK0_IO17 BK0_IO18 GND (Bank 0) BK0_IO19 BK0_IO20 BK0_IO21 BK0_IO22 BK0_IO23 BK0_IO24 BK0_IO25 Second Function HSI0A_SOUTP HSI0A_SOUTN HSI0A_SINP HSI0A_SINN VREF0 HSI0B_SOUTP HSI0B_SOUTN Signal Name NC NC BK0_IO0 BK0_IO1 BK0_IO2 BK0_IO3 BK0_IO4 GND (Bank 0) BK0_IO5 BK0_IO6 BK0_IO7 BK0_IO8 BK0_IO9 BK0_IO10 BK0_IO11 BK0_IO12 GND (Bank 0) BK0_IO13 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC BK0_IO14 BK0_IO15 BK0_IO16 BK0_IO17 BK0_IO18 GND (Bank 0) BK0_IO19 BK0_IO20 BK0_IO21 Second Function HSI0A_SOUTP HSI0A_SOUTN HSI0A_SINP HSI0A_SINN VREF0 HSI0B_SOUTP HSI0B_SOUTN HSI0B_SINP HSI0B_SINN PLL_FBK0 PLL_RST1 PLL_FBK1 PLL_RST0 CLK_OUT0 CLK_OUT1 LVDS Pair/ Polarity 0P 0N 1P 1N 2P 2N 3P 3N 4P 4N 5P 5N 6P 6N 7P 7N 8P 8N 9P 9N 10P 10N HSI0B_SINP HSI0B_SINN PLL_FBK0 PLL_RST1 PLL_FBK1 PLL_RST0 CLK_OUT0 CLK_OUT1 6N 7P 7N 8P 8N 9P 9N 10P 10N 11P 11N 12P 12N 51 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 516-Ball fpBGA (Continued) LFX500 516-Ball BGA Ball R2 R3 R4 T4 T3 T2 T1 U1 U2 U3 V1 V2 V3 V4 W1 Y1 W2 W3 Y2 Y4 Y3 AA1 AA2 AA3 AB2 AC2 AB3 AA4 AC1 AD1 AE1 AF1 AC3 AC4 AD2 AD3 AE2 AF2 AD4 LFX200 LVDS Pair/ Polarity LVDSCLK0 LVDSCLK0 LVDSCLK1 LVDSCLK1 21P 21N 22P 22N 23P 23N 24P 24N 25P 25N 26P 26N 27P 27N 28P 28N 29P 29N 30P 30N 31P 31N 32P 32N 33P 33N 34P 34N 35P 35N 36P 36N 37P LFX125 LVDS Pair/ Polarity LVDSCLK0 LVDSCLK0 LVDSCLK1 LVDSCLK1 13P 13N 14P 14N 15P 15N 16P 16N 17P 17N 18P 18N 19P 19N 20P 20N 21P 21N 22P 22N 23P 23N 24P 24N - Signal Name GCLK0 GCLK1 VCCP0 GNDP0 GCLK2 GCLK3 BK1_IO0 GND (Bank 1) BK1_IO1 BK1_IO2 BK1_IO3 BK1_IO4 BK1_IO5 BK1_IO6 GND (Bank 1) BK1_IO7 BK1_IO8 BK1_IO9 BK1_IO10 BK1_IO11 BK1_IO12 BK1_IO13 BK1_IO14 GND (Bank 1) BK1_IO15 BK1_IO16 BK1_IO17 BK1_IO18 BK1_IO19 BK1_IO20 BK1_IO21 BK1_IO22 GND (Bank 1) BK1_IO23 BK1_IO24 BK1_IO25 BK1_IO26 BK1_IO27 BK1_IO28 BK1_IO29 BK1_IO30 GND (Bank 1) BK1_IO31 BK1_IO32 Second Function CLK_OUT2 CLK_OUT3 SS_CLKOUT0P SS_CLKOUT0N PLL_FBK2 PLL_FBK3 SS_CLKINOP SS_CLKINON PLL_RST2 PLL_RST3 HSI2A_SOUTP HSI2A_SOUTN PLL_RST2 PLL_RST3 HSI2A_SINP HSI2A_SINN VREF1 HSI2B_SOUTP HSI2B_SOUTN HSI2B_SINP HSI2B_SINN - Signal Name GND (Bank 0) GCLK0 GCLK1 VCCP0 GNDP0 GCLK2 GCLK3 GND (Bank 1) BK1_IO0 BK1_IO1 BK1_IO2 BK1_IO3 BK1_IO4 BK1_IO5 NC NC NC NC BK1_IO6 GND (Bank 1) BK1_IO7 BK1_IO8 BK1_IO9 NC NC NC NC BK1_IO10 BK1_IO11 BK1_IO12 BK1_IO13 BK1_IO14 GND (Bank 1) BK1_IO15 BK1_IO16 BK1_IO17 BK1_IO18 BK1_IO19 BK1_IO20 BK1_IO21 BK1_IO22 GND (Bank 1) BK1_IO23 NC Second Function CLK_OUT2 CLK_OUT3 SS_CLKOUT0P SS_CLKOUT0 N PLL_FBK2 PLL_FBK3 SS_CLKIN0P SS_CLKIN0N HSI1A_SOUTP HSI1A_SOUTN PLL_RST2 PLL_RST3 HSI1A_SINP HSI1A_SINN VREF1 HSI1B_SOUTP HSI1B_SOUTN HSI1B_SINP HSI1B_SINN - Signal Name GCLK0 GCLK1 VCCP0 GNDP0 GCLK2 GCLK3 BK1_IO0 BK1_IO1 BK1_IO2 GND (Bank 1) BK1_IO3 BK1_IO4 BK1_IO5 NC NC NC NC BK1_IO6 BK1_IO7 BK1_IO8 GND (Bank 1) BK1_IO9 NC NC NC NC BK1_IO10 BK1_IO11 BK1_IO12 BK1_IO13 NC NC BK1_IO14 BK1_IO15 BK1_IO16 GND (Bank 1) BK1_IO17 BK1_IO18 BK1_IO19 BK1_IO20 BK1_IO21 NC Second Function CLK_OUT2 CLK_OUT3 SS_CLKOUT0P SS_CLKOUT0 N PLL_FBK2 PLL_FBK3 SS_CLKIN0P SS_CLKIN0N PLL_RST2 PLL_RST3 VREF1 - LVDS Pair/ Polarity LVDSCLK0 LVDSCLK0 LVDSCLK1 LVDSCLK1 11P 11N 12P 12N 13P 13N 14P 14N 15P 15N 16P 16N 17P 17N 18P 18N 19P 19N 20P 20N 21P 21N - 52 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 516-Ball fpBGA (Continued) LFX500 516-Ball BGA Ball AE3 AG1 AH1 AG2 AF3 AJ1 AH2 AG3 AF4 AK2 AJ3 AG5 AH4 AK3 AJ4 AH5 AK4 AJ5 AG7 AH6 AK5 AJ6 AG8 AH7 AK6 AJ7 AH8 AG10 AK7 AJ8 AH9 AG11 AK8 AJ9 AH10 AH11 AJ10 AK10 AH12 AJ11 AK11 AJ12 AG13 AH13 LFX200 LVDS Pair/ Polarity 37N 38P 38N 39P 39N 40P 40N 41P 41N 42P 42N 43P 43N 44P 44N 45P 45N 46P 46N 47P 47N 48P 48N 49P 49N 50P 50N 51P 51N 52P 52N 53P 53N 54P 54N 55P 55N 56P 56N 57P 57N LFX125 LVDS Pair/ Polarity 25P 25N 26P 26N 27P 27N 28P 28N 29P 29N 30P 30N 31P 31N 32P Signal Name BK1_IO33 BK1_IO34 BK1_IO35 BK1_IO36 BK1_IO37 BK1_IO38 GND (Bank 1) BK1_IO39 BK1_IO40 BK1_IO41 TCK TMS TOE BK2_IO0 BK2_IO1 BK2_IO2 GND (Bank 2) BK2_IO3 BK2_IO4 BK2_IO5 BK2_IO6 BK2_IO7 BK2_IO8 BK2_IO9 BK2_IO10 GND (Bank 2) BK2_IO11 BK2_IO12 BK2_IO13 BK2_IO14 BK2_IO15 BK2_IO16 BK2_IO17 BK2_IO18 GND (Bank 2) BK2_IO19 BK2_IO20 BK2_IO21 BK2_IO22 BK2_IO23 BK2_IO24 BK2_IO25 BK2_IO26 GND (Bank 2) BK2_IO27 BK2_IO28 BK2_IO29 BK2_IO30 BK2_IO31 Second Function VREF2 - Signal Name NC NC NC NC NC NC NC BK1_IO24 BK1_IO25 TCK TMS TOE BK2_IO0 BK2_IO1 BK2_IO2 GND (Bank 2) BK2_IO3 BK2_IO4 BK2_IO5 BK2_IO6 BK2_IO7 NC NC NC NC NC NC NC NC NC NC NC NC BK2_IO8 BK2_IO9 BK2_IO10 GND (Bank 2) BK2_IO11 BK2_IO12 BK2_IO13 BK2_IO14 BK2_IO15 NC NC BK2_IO16 BK2_IO17 Second Function VREF2 - Signal Name NC NC NC NC NC NC NC NC NC TCK TMS TOE BK2_IO0 BK2_IO1 BK2_IO2 BK2_IO3 BK2_IO4 GND (Bank 2) BK2_IO5 BK2_IO6 BK2_IO7 NC NC NC NC NC NC NC NC NC NC NC NC BK2_IO8 BK2_IO9 BK2_IO10 BK2_IO11 BK2_IO12 BK2_IO13 BK2_IO14 BK2_IO15 NC NC BK2_IO16 BK2_IO17 Second Function VREF2 - LVDS Pair/ Polarity 22P 22N 23P 23N 24P 24N 25P 25N 26P 26N 27P 27N 28P 28N 29P 29N 30P 30N - 32N 33P 33N 34P 34N 53 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 516-Ball fpBGA (Continued) LFX500 516-Ball BGA Ball AJ13 AK12 AK13 AH14 AJ14 AK14 AG15 AH15 AJ15 AK15 AK16 AJ16 AH16 AG16 AK17 AJ17 AH17 AJ18 AH18 AG18 AK18 AK19 AJ19 AH19 AK20 AJ20 AH20 AG20 AK21 AJ21 AH21 AG21 AJ22 AH22 AK23 AJ23 AH23 AK24 AJ24 AG23 AH24 AK25 LFX200 LVDS Pair/ Polarity 58P 58N 59P 59N 60P 60N 61P 61N 62P 62N 63P 63N 64P 64N 65P 65N 66P 66N 67P 67N 68P 68N 69P 69N 70P 70N 71P 71N 72P 72N 73P 73N 74P 74N 75P 75N 76P 76N 77P 77N 78P 78N NC LFX125 LVDS Pair/ Polarity 35P 35N 36P 36N 37P 37N 38P 38N 39P 39N 40P 40N 41P 41N 42P 42N 43P 43N 44P 44N 45P 45N Signal Name BK2_IO32 BK2_IO33 BK2_IO34 GND (Bank 2) BK2_IO35 BK2_IO36 BK2_IO37 BK2_IO38 BK2_IO39 BK2_IO40 BK2_IO41 GND (Bank 2) GND (Bank 3) BK3_IO0 BK3_IO1 BK3_IO2 BK3_IO3 BK3_IO4 BK3_IO5 BK3_IO6 GND (Bank 3) BK3_IO7 BK3_IO8 BK3_IO9 BK3_IO10 BK3_IO11 BK3_IO12 BK3_IO13 BK3_IO14 GND (Bank 3) BK3_IO15 BK3_IO16 BK3_IO17 BK3_IO18 BK3_IO19 BK3_IO20 BK3_IO21 BK3_IO22 GND (Bank 3) BK3_IO23 BK3_IO24 BK3_IO25 BK3_IO26 BK3_IO27 BK3_IO28 BK3_IO29 BK3_IO30 GND (Bank 3) BK3_IO31 Second Function VREF3 - Signal Name BK2_IO18 GND (Bank 2) BK2_IO19 BK2_IO20 BK2_IO21 BK2_IO22 BK2_IO23 BK2_IO24 BK2_IO25 NC NC GND (Bank 2) GND (Bank 3) BK3_IO0 BK3_IO1 BK3_IO2 BK3_IO3 BK3_IO4 BK3_IO5 BK3_IO6 GND (Bank 3) BK3_IO7 BK3_IO8 BK3_IO9 BK3_IO10 BK3_IO11 BK3_IO12 BK3_IO13 BK3_IO14 GND (Bank 3) BK3_IO15 NC NC NC NC BK3_IO16 BK3_IO17 BK3_IO18 BK3_IO19 NC NC NC NC NC NC NC Second Function - Signal Name BK2_IO18 GND (Bank 2) BK2_IO19 BK2_IO20 BK2_IO21 NC NC NC NC NC NC BK3_IO0 BK3_IO1 BK3_IO2 BK3_IO3 BK3_IO4 BK3_IO5 BK3_IO6 BK3_IO7 BK3_IO8 GND (Bank 3) BK3_IO9 BK3_IO10 BK3_IO11 NC NC NC NC NC NC NC NC BK3_IO12 BK3_IO13 BK3_IO14 BK3_IO15 NC NC NC NC NC NC NC NC Second Function VREF3 - LVDS Pair/ Polarity 31P 31N 32P 32N 33P 33N 34P 34N 35P 35N 36P 36N 37P 37N 38P 38N 39P 39N 40P 40N - VREF3 - 46P 46N 47P 47N 48P 48N - 54 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 516-Ball fpBGA (Continued) LFX500 516-Ball BGA Ball AJ25 AG24 AK26 AH25 AJ26 AH26 AK27 AJ27 AG26 AH27 AK28 AJ28 AK29 AH29 AG28 AF27 AF28 AJ30 AH30 AG29 AF29 AE28 AD27 AG30 AF30 AD28 AC27 AE29 AE30 AD29 AD30 AC28 AB28 AA27 AB29 AC29 AC30 AA28 Y27 Y28 AA29 Y29 - LFX200 LVDS Pair/ Polarity 79P 79N 80P 80N 81P 81N 82P 82N 83P 83N 84P 84N 85P 85N 86P 86N 87P 87N 88P 88N 89P 89N 90P 90N 91P 91N 92P 92N 93P 93N 94P 94N 95P 95N 96P 96N 97P 97N 98P - LFX125 LVDS Pair/ Polarity 49P 49N 50P 50N 51P 51N 52P 52N 53P 53N 54P 54N 55P 55N 56P 56N 57P 57N 58P 58N 59P 59N 60P - Signal Name BK3_IO32 BK3_IO33 BK3_IO34 BK3_IO35 BK3_IO36 BK3_IO37 BK3_IO38 GND (Bank 3) BK3_IO39 BK3_IO40 BK3_IO41 RESET DXP DXN BK4_IO0 BK4_IO1 BK4_IO2 GND (Bank 4) BK4_IO3 BK4_IO4 BK4_IO5 BK4_IO6 BK4_IO7 BK4_IO8 BK4_IO9 BK4_IO10 GND (Bank 4) BK4_IO11 BK4_IO12 BK4_IO13 BK4_IO14 BK4_IO15 BK4_IO16 BK4_IO17 BK4_IO18 GND (Bank 4) BK4_IO19 BK4_IO20 BK4_IO21 BK4_IO22 BK4_IO23 BK4_IO24 BK4_IO25 BK4_IO26 GND (Bank 4) BK4_IO27 BK4_IO28 - Second Function HSI3A_SINP HSI3A_SINN HSI3A_SOUTP HSI3A_SOUTN VREF4 HSI3B_SINP HSI3B_SINN PLL_RST4 PLL_RST5 HSI3B_SOUTP HSI3B_SOUTN - Signal Name NC NC BK3_IO20 BK3_IO21 BK3_IO22 GND (Bank 3) BK3_IO23 NC NC BK3_IO24 BK3_IO25 RESET DXP DXN BK4_IO0 BK4_IO1 NC NC NC NC NC NC NC NC BK4_IO2 GND (Bank 4) BK4_IO3 BK4_IO4 BK4_IO5 BK4_IO6 BK4_IO7 BK4_IO8 BK4_IO9 BK4_IO10 GND (Bank 4) BK4_IO11 BK4_IO12 BK4_IO13 BK4_IO14 BK4_IO15 NC NC NC NC BK4_IO16 - Second Function HSI2A_SINP HSI2A_SINN HSI2A_SOUTP HSI2A_SOUTN VREF4 HSI2B_SINP HSI2B_SINN PLL_RST4 PLL_RST5 HSI2B_SOUTP HSI2B_SOUTN - Signal Name NC NC BK3_IO16 GND (Bank 3) BK3_IO17 BK3_IO18 BK3_IO19 NC NC BK3_IO20 BK3_IO21 RESET DXP DXN BK4_IO0 BK4_IO1 NC NC NC NC NC NC NC NC BK4_IO2 BK4_IO3 BK4_IO4 GND (Bank 4) BK4_IO5 NC NC BK4_IO6 BK4_IO7 NC NC BK4_IO8 BK4_IO9 BK4_IO10 BK4_IO11 NC NC NC NC BK4_IO12 GND (Bank 4) Second Function VREF4 PLL_RST4 PLL_RST5 - LVDS Pair/ Polarity 41P 41N 42P 42N 43P 43N 44P 44N 45P 45N 46P 46N 47P 47N 48P 48N 49P 49N 50P - 55 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 516-Ball fpBGA (Continued) LFX500 516-Ball BGA Ball AA30 W28 W29 Y30 W30 V27 V28 V29 V30 U30 U29 U28 T27 T28 T29 T30 R29 R28 R27 R30 P30 P29 P28 N30 N29 N28 N27 M30 M29 L30 L29 M28 L28 K30 K29 L27 K28 H30 G30 J28 K27 LFX200 LVDS Pair/ Polarity 98N 99P 99N 100P 100N 101P 101N 102P 102N 103P 103N 104P 104N LVDSCLK2 LVDSCLK2 LVDSCLK3 LVDSCLK3 105P 105N 106P 106N 107P 107N 108P 108N 109P 109N 110P 110N 111P 111N 112P 112N 113P 113N 114P 114N 115P 115N LFX125 LVDS Pair/ Polarity 60N 61P 61N 62P 62N 63P 63N 64P 64N LVDSCLK2 LVDSCLK2 LVDSCLK3 LVDSCLK3 65P 65N 66P 66N 67P 67N 68P 68N 69P 69N 70P 70N 71P 71N Signal Name BK4_IO29 BK4_IO30 BK4_IO31 BK4_IO32 BK4_IO33 BK4_IO34 GND (Bank 4) BK4_IO35 BK4_IO36 BK4_IO37 BK4_IO38 BK4_IO39 BK4_IO40 GND (Bank 4) BK4_IO41 GCLK4 GCLK5 VCCP1 GNDP1 GCLK6 GCLK7 BK5_IO0 GND (Bank 5) BK5_IO1 BK5_IO2 BK5_IO3 BK5_IO4 BK5_IO5 BK5_IO6 GND (Bank 5) BK5_IO7 BK5_IO8 BK5_IO9 BK5_IO10 BK5_IO11 BK5_IO12 BK5_IO13 BK5_IO14 GND (Bank 5) BK5_IO15 BK5_IO16 BK5_IO17 BK5_IO18 BK5_IO19 BK5_IO20 BK5_IO21 Second Function SS_CLKIN1P SS_CLKIN1N PLL_FBK4 PLL_FBK5 SS_CLKOUT1P SS_CLKOUT1N CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 PLL_RST7 PLL_FBK6 PLL-RST6 PLL_FBK7 HSI4A_SINP HSI4A_SINN HSI4A_SOUTP HSI4A_SOUTN HSI4B_SINP HSI4B_SINN - Signal Name BK4_IO17 BK4_IO18 GND (Bank 4) BK4_IO19 NC NC NC NC BK4_IO20 BK4_IO21 BK4_IO22 BK4_IO23 BK4_IO24 BK4_IO25 GND (Bank 4) GCLK4 GCLK5 VCCP1 GNDP1 GCLK6 GCLK7 GND (Bank 5) BK5_IO0 BK5_IO1 BK5_IO2 BK5_IO3 BK5_IO4 BK5_IO5 BK5_IO6 GND (Bank 5) BK5_IO7 BK5_IO8 BK5_IO9 BK5_IO10 BK5_IO11 BK5_IO12 BK5_IO13 BK5_IO14 GND (Bank 5) BK5_IO15 NC NC NC NC NC NC Second Function SS_CLKIN1P SS_CLKIN1N PLL_FBK4 PLL_FBK5 SS_CLKOUT1P SS_CLKOUT1N CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 PLL_RST7 PLL_FBK6 PLL_RST6 PLL_FBK7 HSI3A_SINP HSI3A_SINN - Signal Name BK4_IO13 BK4_IO14 BK4_IO15 NC NC NC NC BK4_IO16 BK4_IO17 BK4_IO18 BK4_IO19 BK4_IO20 BK4_IO21 GCLK4 GCLK5 VCCP1 GNDP1 GCLK6 GCLK7 BK5_IO0 BK5_IO1 BK5_IO2 GND (Bank 5) BK5_IO3 BK5_IO4 BK5_IO5 BK5_IO6 BK5_IO7 NC NC BK5_IO8 GND (Bank 5) BK5_IO9 BK5_IO10 BK5_IO11 BK5_IO12 BK5_IO13 NC NC NC NC NC NC Second Function SS_CLKIN1P SS_CLKIN1N PLL_FBK4 PLL_FBK5 SS_CLKOUT1P SS_CLKOUT1N CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 PLL_RST7 PLL_FBK6 PLL_RST6 PLL_FBK7 HSI1A_SINP HSI1A_SINN HSI1A_SOUTP HSI1A_SOUTN - LVDS Pair/ Polarity 50N 51P 51N 52P 52N 53P 53N 54P 54N LVDSCLK2 LVDSCLK2 LVDSCLK3 LVDSCLK3 55P 55N 56P 56N 57P 57N 58P 58N 59P 59N 60P 60N 61P 61N - HSI3A_SOUTP HSI3A_SOUTN - 72P 72N - 56 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 516-Ball fpBGA (Continued) LFX500 516-Ball BGA Ball J29 H29 F30 G29 H28 H27 E30 F29 G28 G27 E29 F28 D30 C30 D29 D28 E28 E27 C29 B30 A29 B28 A28 D26 C27 B27 A27 C26 B26 A26 C25 D24 B25 A25 C24 D23 B24 C23 A24 C22 B23 B22 A23 LFX200 LVDS Pair/ Polarity 116P 116N 117P 117N 118P 118N 119P 119N 120P 120N 121P 121N 122P 122N 123P 123N 124P 124N 125P 125N 126P 126N 127P 127N 128P 128N 129P 129N 130P 130N 131P 131N 132P 132N 133P 133N 134P 134N 135P 135N LFX125 LVDS Pair/ Polarity 73P 73N 74P 74N 75P 75N Signal Name BK5_IO22 GND (Bank 5) BK5_IO23 BK5_IO24 BK5_IO25 BK5_IO26 BK5_IO27 BK5_IO28 BK5_IO29 BK5_IO30 GND (Bank 5) BK5_IO31 BK5_IO32 BK5_IO33 BK5_IO34 BK5_IO35 BK5_IO36 BK5_IO37 BK5_IO38 GND (Bank 5) BK5_IO39 BK5_IO40 BK5_IO41 CFG0 DONE PROGRAMb BK6_IO0 BK6_IO1 BK6_IO2 GND (Bank 6) BK6_IO3 BK6_IO4 BK6_IO5 BK6_IO6 BK6_IO7 BK6_IO8 BK6_IO9 BK6_IO10 GND (Bank 6) BK6_IO11 BK6_IO12 BK6_IO13 BK6_IO14 BK6_IO15 BK6_IO16 BK6_IO17 BK6_IO18 GND (Bank 6) BK6_IO19 Second Function HSI4B_SOUTP HSI4B_SOUTN HSI5A_SINP HSI5A_SINN HSI5A_SOUTP HSI5A_SOUTN VREF5 HSI5B_SINP HSI5B_SINN HSI5B_SOUTP HSI5B_SOUTN INITb CCLK CSb Read DATA7 DATA6 Signal Name NC NC NC NC NC NC NC NC NC NC BK5_IO16 BK5_IO17 BK5_IO18 BK5_IO19 BK5_IO20 BK5_IO21 BK5_IO22 GND (Bank 5) BK5_IO23 BK5_IO24 BK5_IO25 CFG0 DONE PROGRAMb BK6_IO0 BK6_IO1 BK6_IO2 GND (Bank 6) BK6_IO3 BK6_IO4 BK6_IO5 NC NC NC NC NC NC NC NC NC NC NC NC BK6_IO6 BK6_IO7 Second Function VREF5 HSI3B_SINP HSI3B_SINN Signal Name NC NC NC NC NC NC NC NC NC NC BK5_IO14 BK5_IO15 BK5_IO16 GND (Bank 5) BK5_IO17 NC NC BK5_IO20 BK5_IO21 BK5_IO18 BK5_IO19 CFG0 DONE PROGRAMb BK6_IO0 BK6_IO1 BK6_IO2 BK6_IO3 BK6_IO4 GND (Bank 6) BK6_IO5 NC NC NC NC NC NC NC NC NC NC NC NC BK6_IO6 BK6_IO7 Second Function VREF5 HSI1B_SINP HSI1B_SINN HSI1B_SOUTP HSI1B_SOUTN INITb CCLK CSb Read DATA7 DATA6 LVDS Pair/ Polarity 62P 62N 63P 63N 65P 65N 64P 64N 66P 66N 67P 67N 68P 68N 69P 69N HSI3B_SOUTP HSI3B_SOUTN INITb CCLK CSb Read DATA7 DATA6 76P 76N 77P 77N 78P 78N 79P 79N 80P 80N 81P 81N 57 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 516-Ball fpBGA (Continued) LFX500 516-Ball BGA Ball D21 C21 B21 A21 D20 C20 B20 A20 C19 B19 A19 A18 D18 C18 B18 C17 B17 A17 D16 C16 B16 A16 A15 B15 C15 D15 A14 B14 C14 A13 B13 C13 D13 B12 C12 A12 A11 B11 C11 D11 LFX200 LVDS Pair/ Polarity 136P 136N 137P 137N 138P 138N 139P 139N 140P 140N 141P 141N 142P 142N 143P 143N 144P 144N 145P 145N 146P 146N 147P 147N 148P 148N 149P 149N 150P 150N 151P 151N 152P 152N 153P 153N 154P 154N 155P 155N LFX125 LVDS Pair/ Polarity 82P 82N 83P 83N 84P 84N 85P 85N 86P 86N Signal Name BK6_IO20 BK6_IO21 BK6_IO22 BK6_IO23 BK6_IO24 BK6_IO25 BK6_IO26 GND (Bank 6) BK6_IO27 BK6_IO28 BK6_IO29 BK6_IO30 BK6_IO31 BK6_IO32 BK6_IO33 BK6_IO34 GND (Bank 6) BK6_IO35 BK6_IO36 BK6_IO37 BK6_IO38 BK6_IO39 BK6_IO40 BK6_IO41 GND (Bank 6) GND (Bank 7) BK7_IO0 BK7_IO1 BK7_IO2 BK7_IO3 BK7_IO4 BK7_IO5 BK7_IO6 GND (Bank 7) BK7_IO7 BK7_IO8 BK7_IO9 BK7_IO10 BK7_IO11 BK7_IO12 BK7_IO13 BK7_IO14 GND (Bank 7) BK7_IO15 BK7_IO16 BK7_IO17 Second Function VREF6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 - Signal Name BK6_IO8 BK6_IO9 BK6_IO10 GND (Bank 6) BK6_IO11 BK6_IO12 BK6_IO13 BK6_IO14 BK6_IO15 BK6_IO16 BK6_IO17 BK6_IO18 GND (Bank 6) BK6_IO19 BK6_IO20 BK6_IO21 BK6_IO22 BK6_IO23 NC NC NC NC BK6_IO24 BK6_IO25 GND (Bank 6) GND (Bank 7) BK7_IO0 BK7_IO1 BK7_IO2 BK7_IO3 BK7_IO4 BK7_IO5 BK7_IO6 GND (Bank 7) BK7_IO7 BK7_IO8 BK7_IO9 BK7_IO10 BK7_IO11 BK7_IO12 BK7_IO13 BK7_IO14 GND (Bank 7) BK7_IO15 NC NC Second Function VREF6 DATA5 DATA4 DATA3 DATA2 Signal Name BK6_IO8 BK6_IO9 BK6_IO10 BK6_IO11 BK6_IO12 GND (Bank 6) BK6_IO13 BK6_IO14 BK6_IO15 BK6_IO16 BK6_IO17 BK6_IO18 GND (Bank 6) BK6_IO19 BK6_IO20 BK6_IO21 NC NC NC NC NC NC NC NC BK7_IO0 BK7_IO1 BK7_IO2 GND (Bank 7) BK7_IO3 BK7_IO4 BK7_IO5 NC NC NC NC BK7_IO6 BK7_IO7 BK7_IO8 GND (Bank 7) BK7_IO9 BK7_IO10 BK7_IO11 NC NC Second Function VREF6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 - LVDS Pair/ Polarity 70P 70N 71P 71N 72P 72N 73P 73N 74P 74N 75P 75N 76P 76N 77P 77N 78P 78N 79P 79N 80P 80N 81P 81N 82P 82N - DATA1 DATA0 87P 87N 88P 88N 89P - 89N - 90P 90N 91P 91N 92P 92N 93P 93N 94P 94N 95P 95N 96P 96N 97P 97N - 98P 98N - 58 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 516-Ball fpBGA (Continued) LFX500 516-Ball BGA Ball A10 B10 C10 D10 B9 C9 A8 B8 C8 D8 A7 B7 C7 D7 A6 B6 B5 C6 A5 A4 B4 C5 A3 A2 D5 C4 B3 LFX200 LVDS Pair/ Polarity 156P 156N 157P 157N 158P 158N 159P 159N 160P 160N 161P 161N 162P 162N 163P 163N 164P 164N 165P 165N 166P 166N 167P 167N - LFX125 LVDS Pair/ Polarity 99P 99N 100P 100N 101P 101N 102P 102N 103P 103N - Signal Name BK7_IO18 BK7_IO19 BK7_IO20 BK7_IO21 BK7_IO22 GND (Bank 7) BK7_IO23 BK7_IO24 BK7_IO25 BK7_IO26 BK7_IO27 BK7_IO28 BK7_IO29 BK7_IO30 GND (Bank 7) BK7_IO31 BK7_IO32 BK7_IO33 BK7_IO34 BK7_IO35 BK7_IO36 BK7_IO37 BK7_IO38 GND (Bank 7) BK7_IO39 BK7_IO40 BK7_IO41 TDO VCCJ TDI Second Function VREF7 - Signal Name NC NC BK7_IO16 BK7_IO17 BK7_IO18 BK7_IO19 BK7_IO20 BK7_IO21 NC NC NC NC NC NC NC NC NC NC NC NC BK7_IO22 GND (Bank 7) BK7_IO23 BK7_IO24 BK7_IO25 TDO VCCJ TDI Second Function VREF7 - Signal Name NC NC BK7_IO12 BK7_IO13 BK7_IO14 BK7_IO15 BK7_IO16 GND (Bank 7) BK7_IO17 NC NC NC NC NC NC NC NC NC NC NC NC BK7_IO18 BK7_IO19 BK7_IO20 BK7_IO21 TDO VCCJ TDI Second Function VREF7 - LVDS Pair/ Polarity 83P 83N 84P 84N 85P 85N 86P 86N 87P 87N - 59 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA LFX1200 680-Ball fpBGA C4 B4 E6 D6 A4 E8 C5 C6 A6 A5 B6 B5 B7 A7 D8 D7 D9 E10 C8 C7 A8 A9 C9 B8 B9 B10 D11 D10 A10 C12 D12 C11 A12 A13 B13 B12 E14 Signal Name BK0_IO0 BK0_IO1 BK0_IO2 GND (Bank 0) BK0_IO3 BK0_IO4 BK0_IO5 BK0_IO6 BK0_IO7 BK0_IO8 BK0_IO9 BK0_IO10 GND (Bank 0) BK0_IO11 BK0_IO12 BK0_IO13 BK0_IO14 BK0_IO15 BK0_IO16 BK0_IO17 BK0_IO18 GND (Bank 0) BK0_IO19 BK0_IO20 BK0_IO21 BK0_IO22 BK0_IO23 BK0_IO24 BK0_IO25 BK0_IO26 GND (Bank 0) BK0_IO27 BK0_IO28 BK0_IO29 BK0_IO30 BK0_IO31 BK0_IO32 BK0_IO33 BK0_IO34 GND (Bank 0) BK0_IO35 BK0_IO36 Second Function HSI0A_SOUTP HSI0A_SOUTN HSI0A_SINP HSI0A_SINN VREF0 HSI0B_SOUTP HSI0B_SOUTN HSI0B_SINP HSI0B_SINN HSI1A_SOUTP HSI1A_SOUTN HSI1A_SINP HSI1A_SINN HSI1B_SOUTP HSI1B_SOUTN HSI1B_SINP HSI1B_SINN 1N 2P 2N 3P 3N 4P 4N 5P 5N 6P 6N 7P 7N 8P 8N 9P 9N 10P 10N 11P 11N 12P 12N 13P 13N 14P 14N 15P 15N 16P 16N 17P 17N 18P LVDS Pair Polarity 0P 0N 1P 60 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Continued) LFX1200 680-Ball fpBGA D14 C13 D13 B14 A14 C15 D15 A15 C16 B15 B16 A16 B17 D16 E16 D17 C17 A18 D18 A17 E19 A19 B19 C18 B18 D19 C19 E20 A21 B21 C21 B23 C23 B22 C22 D21 E21 B24 Signal Name BK0_IO37 BK0_IO38 BK0_IO39 BK0_IO40 BK0_IO41 BK0_IO42 GND (Bank 0) BK0_IO43 BK0_IO44 BK0_IO45 BK0_IO46 BK0_IO47 BK0_IO48 BK0_IO49 BK0_IO50 GND (Bank 0) BK0_IO51 BK0_IO52 BK0_IO53 BK0_IO54 BK0_IO55 BK0_IO56 BK0_IO57 BK0_IO58 GND (Bank 0) BK0_IO59 BK0_IO60 BK0_IO61 GND (Bank 0) GCLK0 GCLK1 VCCP0 GNDP0 GCLK2 GCLK3 BK1_IO0 BK1_IO1 BK1_IO2 GND (Bank 1) BK1_IO3 BK1_IO4 BK1_IO5 BK1_IO6 Second Function HSI2A_SOUTP HSI2A_SOUTN HSI2A_SINP HSI2A_SINN HSI2B_SOUTP HSI2B_SOUTN HSI2B_SINP HSI2B_SINN PLL_RST0 PLL_RST1 PLL_FBK0 PLL_FBK1 CLK_OUT0 CLK_OUT1 CLK_OUT2 CLK_OUT3 SS_CLKOUT0P SS_CLKOUT0N PLL_FBK2 PLL_FBK3 SS_CLKIN0P LVDS Pair Polarity 18N 19P 19N 20P 20N 21P 21N 22P 22N 23P 23N 24P 24N 25P 25N 26P 26N 27P 27N 28P 28N 29P 29N 30P 30N LVDSCLK0 LVDSCLK0 LVDSCLK1 LVDSCLK1 31P 31N 32P 32N 33P 33N 34P 61 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Continued) LFX1200 680-Ball fpBGA C24 A22 D22 A23 B25 D23 A24 A25 E24 D24 A26 D25 C25 B26 B27 D26 A27 A28 E26 C27 D27 B28 A30 C28 D28 A31 B30 E28 D29 C29 B31 D30 E30 A32 C31 D31 C32 B32 Signal Name BK1_IO7 BK1_IO8 BK1_IO9 BK1_IO10 GND (Bank 1) BK1_IO11 BK1_IO12 BK1_IO13 BK1_IO14 BK1_IO15 BK1_IO16 BK1_IO17 BK1_IO18 GND (Bank 1) BK1_IO19 BK1_IO20 BK1_IO21 BK1_IO22 BK1_IO23 BK1_IO24 BK1_IO25 BK1_IO26 GND (Bank 1) BK1_IO27 BK1_IO28 BK1_IO29 BK1_IO30 BK1_IO31 BK1_IO32 BK1_IO33 BK1_IO34 GND (Bank 1) BK1_IO35 BK1_IO36 BK1_IO37 BK1_IO38 BK1_IO39 BK1_IO40 BK1_IO41 BK1_IO42 GND (Bank 1) BK1_IO43 BK1_IO44 Second Function SS_CLKIN0N PLL_RST2 PLL_RST3 HSI3A_SOUTP HSI3A_SOUTN HSI3A_SINP HSI3A_SINN HSI3B_SOUTP HSI3B_SOUTN HSI3B_SINP HSI3B_SINN HSI4A_SOUTP HSI4A_SOUTN LVDS Pair Polarity 34N 35P 35N 36P 36N 37P 37N 38P 38N 39P 39N 40P 40N 41P 41N 42P 42N 43P 43N 44P 44N 45P 45N 46P 46N 47P 47N 48P 48N 49P 49N 50P 50N 51P 51N 52P 52N 53P 62 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Continued) LFX1200 680-Ball fpBGA A33 C33 B33 A34 A35 D32 D33 E32 C34 B34 B35 A36 D34 C35 E34 B36 C36 D39 D37 D38 E37 F35 E39 F39 F36 E38 G38 F37 G36 G39 H35 F38 J37 H36 G37 H37 H39 K35 J36 Signal Name BK1_IO45 BK1_IO46 BK1_IO47 BK1_IO48 BK1_IO49 BK1_IO50 GND (Bank 1) BK1_IO51 BK1_IO52 BK1_IO53 BK1_IO54 BK1_IO55 BK1_IO56 BK1_IO57 BK1_IO58 GND (Bank 1) BK1_IO59 BK1_IO60 BK1_IO61 TCK TMS TOE BK2_IO0 BK2_IO1 BK2_IO2 GND (Bank 2) BK2_IO3 BK2_IO4 BK2_IO5 BK2_IO6 BK2_IO7 BK2_IO8 BK2_IO9 BK2_IO10 GND (Bank 2) BK2_IO11 BK2_IO12 BK2_IO13 BK2_IO14 BK2_IO15 BK2_IO16 BK2_IO17 BK2_IO18 Second Function HSI4A_SINP HSI4A_SINN VREF1 HSI4B_SOUTP HSI4B_SOUTN HSI4B_SINP HSI4B_SINN VREF2 LVDS Pair Polarity 53N 54P 54N 55P 55N 56P 56N 57P 57N 58P 58N 59P 59N 60P 60N 61P 61N 62P 62N 63P 63N 64P 64N 65P 65N 66P 66N 67P 67N 68P 68N 69P 69N 70P 70N 71P 63 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Continued) LFX1200 680-Ball fpBGA K36 H38 J38 J39 L36 K38 M36 L37 K39 L38 P35 N36 M37 L39 M38 M39 P36 R36 N37 P38 T35 R37 R38 P39 R39 T38 T36 T37 U36 U37 T39 V36 U38 U39 V38 V37 W36 W35 Signal Name GND (Bank 2) BK2_IO19 BK2_IO20 BK2_IO21 BK2_IO22 BK2_IO23 BK2_IO24 BK2_IO25 BK2_IO26 GND (Bank 2) BK2_IO27 BK2_IO28 BK2_IO29 BK2_IO30 BK2_IO31 BK2_IO32 BK2_IO33 BK2_IO34 GND (Bank 2) BK2_IO35 BK2_IO36 BK2_IO37 BK2_IO38 BK2_IO39 BK2_IO40 BK2_IO41 BK2_IO42 GND (Bank 2) BK2_IO43 BK2_IO44 BK2_IO45 BK2_IO46 BK2_IO47 BK2_IO48 BK2_IO49 BK2_IO50 GND (Bank 2) BK2_IO51 BK2_IO52 BK2_IO53 BK2_IO54 BK2_IO55 BK2_IO56 Second Function LVDS Pair Polarity 71N 72P 72N 73P 73N 74P 74N 75P 75N 76P 76N 77P 77N 78P 78N 79P 79N 80P 80N 81P 81N 82P 82N 83P 83N 84P 84N 85P 85N 86P 86N 87P 87N 88P 88N 89P 89N 90P 64 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Continued) LFX1200 680-Ball fpBGA V39 W37 W38 W39 AA39 AA38 Y35 AA37 AA35 AB39 AB38 AA36 AB37 AC39 AC38 AB36 AC37 AC36 AD39 AD37 AD36 AD35 AE38 AD38 AE39 AF38 AF37 AF39 AE36 AF36 AG38 AG39 AG37 AH37 AH38 AG36 Signal Name BK2_IO57 BK2_IO58 GND (Bank 2) BK2_IO59 BK2_IO60 BK2_IO61 GND (Bank 2) GND (Bank 3) BK3_IO0 BK3_IO1 BK3_IO2 GND (Bank 3) BK3_IO3 BK3_IO4 BK3_IO5 BK3_IO6 BK3_IO7 BK3_IO8 BK3_IO9 BK3_IO10 GND (Bank 3) BK3_IO11 BK3_IO12 BK3_IO13 BK3_IO14 BK3_IO15 BK3_IO16 BK3_IO17 BK3_IO18 GND (Bank 3) BK3_IO19 BK3_IO20 BK3_IO21 BK3_IO22 BK3_IO23 BK3_IO24 BK3_IO25 BK3_IO26 GND (Bank 3) BK3_IO27 BK3_IO28 BK3_IO29 BK3_IO30 Second Function LVDS Pair Polarity 90N 91P 91N 92P 92N 93P 93N 94P 94N 95P 95N 96P 96N 97P 97N 98P 98N 99P 99N 100P 100N 101P 101N 102P 102N 103P 103N 104P 104N 105P 105N 106P 106N 107P 107N 108P 65 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Continued) LFX1200 680-Ball fpBGA AH39 AK39 AK38 AF35 AJ37 AH36 AM39 AL38 AL39 AJ36 AH35 AL37 AN38 AM38 AK36 AM37 AN37 AN39 AL36 AK35 AP39 AM36 AP38 AR39 AN36 AM35 AR38 AP37 AT39 AR37 AP36 AT38 AP35 AT37 AU36 AV36 AR34 AW36 Signal Name BK3_IO31 BK3_IO32 BK3_IO33 BK3_IO34 GND (Bank 3) BK3_IO35 BK3_IO36 BK3_IO37 BK3_IO38 BK3_IO39 BK3_IO40 BK3_IO41 BK3_IO42 GND (Bank 3) BK3_IO43 BK3_IO44 BK3_IO45 BK3_IO46 BK3_IO47 BK3_IO48 BK3_IO49 BK3_IO50 GND (Bank 3) BK3_IO51 BK3_IO52 BK3_IO53 BK3_IO54 BK3_IO55 BK3_IO56 BK3_IO57 BK3_IO58 GND (Bank 3) BK3_IO59 BK3_IO60 BK3_IO61 RESET DXP DXN BK4_IO0 BK4_IO1 BK4_IO2 GND (Bank 4) BK4_IO3 Second Function VREF3 LVDS Pair Polarity 108N 109P 109N 110P 110N 111P 111N 112P 112N 113P 113N 114P 114N 115P 115N 116P 116N 117P 117N 118P 118N 119P 119N 120P 120N 121P 121N 122P 122N 123P 123N 124P 124N 125P 125N 66 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Continued) LFX1200 680-Ball fpBGA AW35 AV35 AV34 AU34 AT34 AU35 AT33 AU33 AW34 AV33 AR32 AT32 AU32 AW33 AV32 AV31 AU31 AW32 AR30 AT31 AW31 AV30 AT30 AT29 AW30 AU29 AT28 AU28 AV28 AT27 AU27 AV27 AW28 AR26 AW27 AT26 AV26 AR24 AT25 Signal Name BK4_IO4 BK4_IO5 BK4_IO6 BK4_IO7 BK4_IO8 BK4_IO9 BK4_IO10 GND (Bank 4) BK4_IO11 BK4_IO12 BK4_IO13 BK4_IO14 BK4_IO15 BK4_IO16 BK4_IO17 BK4_IO18 GND (Bank 4) BK4_IO19 BK4_IO20 BK4_IO21 BK4_IO22 BK4_IO23 BK4_IO24 BK4_IO25 BK4_IO26 GND (Bank 4) BK4_IO27 BK4_IO28 BK4_IO29 BK4_IO30 BK4_IO31 BK4_IO32 BK4_IO33 BK4_IO34 GND (Bank 4) BK4_IO35 BK4_IO36 BK4_IO37 BK4_IO38 BK4_IO39 BK4_IO40 BK4_IO41 BK4_IO42 Second Function HSI5A_SINP HSI5A_SINN HSI5A_SOUTP HSI5A_SOUTN VREF4 HSI5B_SINP HSI5B_SINN HSI5B_SOUTP HSI5B_SOUTN HSI6A_SINP HSI6A_SINN HSI6A_SOUTP HSI6A_SOUTN HSI6B_SINP HSI6B_SINN HSI6B_SOUTP HSI6B_SOUTN LVDS Pair Polarity 126P 126N 127P 127N 128P 128N 129P 129N 130P 130N 131P 131N 132P 132N 133P 133N 134P 134N 135P 135N 136P 136N 137P 137N 138P 138N 139P 139N 140P 140N 141P 141N 142P 142N 143P 143N 144P 144N 145P 67 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Continued) LFX1200 680-Ball fpBGA AW26 AV25 AT24 AU24 AU25 AW25 AW24 AU23 AT23 AV24 AW23 AV23 AU22 AR21 AT22 AV22 AV21 AT21 AU21 AT19 AU19 AW22 AR20 AU18 AT18 AV17 AV18 AW21 AV19 AR19 AW19 AW18 AW17 AT17 AV16 AU17 Signal Name GND (Bank 4) BK4_IO43 BK4_IO44 BK4_IO45 BK4_IO46 BK4_IO47 BK4_IO48 BK4_IO49 BK4_IO50 GND (Bank 4) BK4_IO51 BK4_IO52 BK4_IO53 BK4_IO54 BK4_IO55 BK4_IO56 BK4_IO57 BK4_IO58 GND (Bank 4) BK4_IO59 BK4_IO60 BK4_IO61 GND (Bank 4) GCLK4 GCLK5 VCCP1 GNDP1 GCLK6 GCLK7 GND (Bank 5) BK5_IO0 BK5_IO1 BK5_IO2 GND (Bank 5) BK5_IO3 BK5_IO4 BK5_IO5 BK5_IO6 BK5_IO7 BK5_IO8 BK5_IO9 BK5_IO10 GND (Bank 5) Second Function PLL_RST4 PLL_RST5 SS_CLKIN1P SS_CLKIN1N PLL_FBK4 PLL_FBK5 SS_CLKOUT1P SS_CLKOUT1N CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 PLL_FBK6 PLL_FBK7 PLL_RST6 PLL_RST7 HSI7A_SINP LVDS Pair Polarity 145N 146P 146N 147P 147N 148P 148N 149P 149N 150P 150N 151P 151N 152P 152N 153P 153N 154P 154N LVDSCLK2 LVDSCLK2 LVDSCLK3 LVDSCLK3 155P 155N 156P 156N 157P 157N 158P 158N 159P 159N 160P - 68 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Continued) LFX1200 680-Ball fpBGA AT16 AW16 AU16 AV14 AV15 AU15 AW15 AT15 AR16 AW14 AW13 AR14 AT14 AT13 AV13 AU12 AU13 AV12 AT12 AR12 AT11 AW12 AU11 AV9 AV10 AW10 AW9 AT10 AU9 AT9 AR10 AU8 AV8 AW8 AW7 AU7 AT8 AV7 AW6 Signal Name BK5_IO11 BK5_IO12 BK5_IO13 BK5_IO14 BK5_IO15 BK5_IO16 BK5_IO17 BK5_IO18 GND (Bank 5) BK5_IO19 BK5_IO20 BK5_IO21 BK5_IO22 BK5_IO23 BK5_IO24 BK5_IO25 BK5_IO26 GND (Bank 5) BK5_IO27 BK5_IO28 BK5_IO29 BK5_IO30 BK5_IO31 BK5_IO32 BK5_IO33 BK5_IO34 GND (Bank 5) BK5_IO35 BK5_IO36 BK5_IO37 BK5_IO38 BK5_IO39 BK5_IO40 BK5_IO41 BK5_IO42 GND (Bank 5) BK5_IO43 BK5_IO44 BK5_IO45 BK5_IO46 BK5_IO47 BK5_IO48 BK5_IO49 Second Function HSI7A_SINN HSI7A_SOUTP HSI7A_SOUTN HSI7B_SINP HSI7B_SINN HSI7B_SOUTP HSI7B_SOUTN HSI8A_SINP HSI8A_SINN HSI8A_SOUTP HSI8A_SOUTN HSI8B_SINP HSI8B_SINN HSI8B_SOUTP HSI8B_SOUTN HSI9A_SINP HSI9A_SINN HSI9A_SOUTP HSI9A_SOUTN VREF5 LVDS Pair Polarity 160N 161P 161N 162P 162N 163P 163N 164P 164N 165P 165N 166P 166N 167P 167N 168P 168N 169P 169N 170P 170N 171P 171N 172P 172N 173P 173N 174P 174N 175P 175N 176P 176N 177P 177N 178P 178N 179P 179N 69 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Continued) LFX1200 680-Ball fpBGA AU6 AV6 AR8 AT7 AU5 AV5 AW5 AW4 AT6 AV4 AR6 AU4 AT1 AT3 AT2 AP4 AP5 AR3 AR2 AP3 AR1 AP2 AP1 AN4 AM5 AN3 AN2 AM4 AM3 AN1 AM2 AL4 AK5 AM1 AK4 AL3 AL2 AL1 Signal Name BK5_IO50 GND (Bank 5) BK5_IO51 BK5_IO52 BK5_IO53 BK5_IO54 BK5_IO55 BK5_IO56 BK5_IO57 BK5_IO58 GND (Bank 5) BK5_IO59 BK5_IO60 BK5_IO61 CFG0 DONE PROGRAMb BK6_IO0 BK6_IO1 BK6_IO2 GND (Bank 6) BK6_IO3 BK6_IO4 BK6_IO5 BK6_IO6 BK6_IO7 BK6_IO8 BK6_IO9 BK6_IO10 GND (Bank 6) BK6_IO11 BK6_IO12 BK6_IO13 BK6_IO14 BK6_IO15 BK6_IO16 BK6_IO17 BK6_IO18 GND (Bank 6) BK6_IO19 BK6_IO20 BK6_IO21 BK6_IO22 Second Function HSI9B_SINP HSI9B_SINN HSI9B_SOUTP HSI9B_SOUTN INITb CCLK CSb Read VREF6 LVDS Pair Polarity 180P 180N 181P 181N 182P 182N 183P 183N 184P 184N 185P 185N 186P 186N 187P 187N 188P 188N 189P 189N 190P 190N 191P 191N 192P 192N 193P 193N 194P 194N 195P 195N 196P 196N 197P 70 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Continued) LFX1200 680-Ball fpBGA AK2 AK1 AJ4 AJ3 AH4 AH3 AH2 AH1 AG4 AF5 AG3 AG2 AF4 AF3 AG1 AE2 AF1 AF2 AE1 AE4 AD4 AD5 AD3 AD2 AD1 AC4 AC3 AC2 AC1 AB3 AB4 AB2 AB1 AA3 AA4 AA5 AA2 AA1 Signal Name BK6_IO23 BK6_IO24 BK6_IO25 BK6_IO26 GND (Bank 6) BK6_IO27 BK6_IO28 BK6_IO29 BK6_IO30 BK6_IO31 BK6_IO32 BK6_IO33 BK6_IO34 GND (Bank 6) BK6_IO35 BK6_IO36 BK6_IO37 BK6_IO38 BK6_IO39 BK6_IO40 BK6_IO41 BK6_IO42 GND (Bank 6) BK6_IO43 BK6_IO44 BK6_IO45 BK6_IO46 BK6_IO47 BK6_IO48 BK6_IO49 BK6_IO50 GND (Bank 6) BK6_IO51 BK6_IO52 BK6_IO53 BK6_IO54 BK6_IO55 BK6_IO56 BK6_IO57 BK6_IO58 GND (Bank 6) BK6_IO59 BK6_IO60 Second Function DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 LVDS Pair Polarity 197N 198P 198N 199P 199N 200P 200N 201P 201N 202P 202N 203P 203N 204P 204N 205P 205N 206P 206N 207P 207N 208P 208N 209P 209N 210P 210N 211P 211N 212P 212N 213P 213N 214P 214N 215P 215N 216P 71 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Continued) LFX1200 680-Ball fpBGA Y5 W3 W1 W2 W4 V1 V2 V3 V4 W5 U1 U2 U3 U4 T1 T2 T3 R1 R2 T4 P1 P2 P3 R4 T5 M1 M2 N3 P4 L1 M3 L2 N4 K1 K2 P5 Signal Name BK6_IO61 GND (Bank 6) GND (Bank 7) BK7_IO0 BK7_IO1 BK7_IO2 GND (Bank 7) BK7_IO3 BK7_IO4 BK7_IO5 BK7_IO6 BK7_IO7 BK7_IO8 BK7_IO9 BK7_IO10 GND (Bank 7) BK7_IO11 BK7_IO12 BK7_IO13 BK7_IO14 BK7_IO15 BK7_IO16 BK7_IO17 BK7_IO18 GND (Bank 7) BK7_IO19 BK7_IO20 BK7_IO21 BK7_IO22 BK7_IO23 BK7_IO24 BK7_IO25 BK7_IO26 GND (Bank 7) BK7_IO27 BK7_IO28 BK7_IO29 BK7_IO30 BK7_IO31 BK7_IO32 BK7_IO33 BK7_IO34 GND (Bank 7) Second Function LVDS Pair Polarity 216N 217P 217N 218P 218N 219P 219N 220P 220N 221P 221N 222P 222N 223P 223N 224P 224N 225P 225N 226P 226N 227P 227N 228P 228N 229P 229N 230P 230N 231P 231N 232P 232N 233P 233N 234P - 72 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Continued) LFX1200 680-Ball fpBGA L3 J1 J2 M4 H1 J3 L4 M5 H2 K4 G1 H3 J4 K5 G3 H4 F2 G2 H5 F3 F1 G4 E1 F4 E2 F5 E3 D2 D3 D1 Signal Name BK7_IO35 BK7_IO36 BK7_IO37 BK7_IO38 BK7_IO39 BK7_IO40 BK7_IO41 BK7_IO42 GND (Bank 7) BK7_IO43 BK7_IO44 BK7_IO45 BK7_IO46 BK7_IO47 BK7_IO48 BK7_IO49 BK7_IO50 GND (Bank 7) BK7_IO51 BK7_IO52 BK7_IO53 BK7_IO54 BK7_IO55 BK7_IO56 BK7_IO57 BK7_IO58 GND (Bank 7) BK7_IO59 BK7_IO60 BK7_IO61 TDO VCCJ TDI Second Function VREF7 LVDS Pair Polarity 234N 235P 235N 236P 236N 237P 237N 238P 238N 239P 239N 240P 240N 241P 241N 242P 242N 243P 243N 244P 244N 245P 245N 246P 246N 247P 247N - 73 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA LFX1200 900 fpBGA Ball D3 E3 C2 C1 E4 F5 D2 D1 F4 F3 E2 E1 G6 G5 F1 F2 G4 G3 G2 G1 H3 H4 H1 H2 J7 J6 J1 J2 J4 J5 K1 K2 K5 K4 L1 Signal Name BK0_IO0 BK0_IO1 BK0_IO2 GND (Bank 0) BK0_IO3 BK0_IO4 BK0_IO5 BK0_IO6 BK0_IO7 BK0_IO8 BK0_IO9 BK0_IO10 GND (Bank 0) BK0_IO11 BK0_IO12 BK0_IO13 BK0_IO14 BK0_IO15 BK0_IO16 BK0_IO17 BK0_IO18 GND (Bank 0) BK0_IO19 BK0_IO20 BK0_IO21 BK0_IO22 BK0_IO23 BK0_IO24 BK0_IO25 BK0_IO26 GND (Bank 0) BK0_IO27 BK0_IO28 BK0_IO29 BK0_IO30 BK0_IO31 BK0_IO32 BK0_IO33 BK0_IO34 GND (Bank 0) Second Function HSI0A_SOUTP HSI0A_SOUTN HSI0A_SINP HSI0A_SINN VREF0 HSI0B_SOUTP HSI0B_SOUTN HSI0B_SINP HSI0B_SINN HSI1A_SOUTP HSI1A_SOUTN HSI1A_SINP HSI1A_SINN HSI1B_SOUTP HSI1B_SOUTN HSI1B_SINP LVDS Pair/ Polarity 0P 0N 1P 1N 2P 2N 3P 3N 4P 4N 5P 5N 6P 6N 7P 7N 8P 8N 9P 9N 10P 10N 11P 11N 12P 12N 13P 13N 14P 14N 15P 15N 16P 16N 17P Signal Name NC NC NC NC BK0_IO0 BK0_IO1 BK0_IO2 GND (Bank 0) BK0_IO3 BK0_IO4 BK0_IO5 BK0_IO6 BK0_IO7 BK0_IO9 BK0_IO8 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC BK0_IO10 GND (Bank 0) BK0_IO11 BK0_IO12 BK0_IO13 BK0_IO14 LFX500 Second Function HSI0A_SOUTP HSI0A_SOUTN HSI0A_SINP HSI0A_SINN VREF0 HSI0B_SOUTP HSI0B_SOUTN HSI0B_SINP LVDS Pair/ Polarity 0P 0N 1P 1N 2P 2N 3P 3N 4N 4P 5P 5N 6P 6N 7P - 74 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Continued) LFX1200 900 fpBGA Ball L2 L6 L5 M1 M2 L3 L4 M6 M5 M4 M3 N1 N2 N7 N6 P1 P2 N3 N4 P6 P5 P3 P4 R7 R6 R1 R2 R3 R4 R5 T3 T4 T5 T2 Signal Name BK0_IO35 BK0_IO36 BK0_IO37 BK0_IO38 BK0_IO39 BK0_IO40 BK0_IO41 BK0_IO42 GND (Bank 0) BK0_IO43 BK0_IO44 BK0_IO45 BK0_IO46 BK0_IO47 BK0_IO48 BK0_IO49 BK0_IO50 GND (Bank 0) BK0_IO51 BK0_IO52 BK0_IO53 BK0_IO54 BK0_IO55 BK0_IO56 BK0_IO57 BK0_IO58 GND (Bank 0) BK0_IO59 BK0_IO60 BK0_IO61 GND (Bank 0) GCLK0 GCLK1 VCCP0 GNDP0 GCLK2 GCLK3 GND (Bank 1) BK1_IO0 Second Function HSI1B_SINN HSI2A_SOUTP HSI2A_SOUTN HSI2A_SINP HSI2A_SINN HSI2B_SOUTP HSI2B_SOUTN HSI2B_SINP HSI2B_SINN PLL_RST0 PLL_RST1 PLL_FBK0 PLL_FBK1 CLK_OUT0 CLK_OUT1 CLK_OUT2 LVDS Pair/ Polarity 17N 18P 18N 19P 19N 20P 20N 21P 21N 22P 22N 23P 23N 24P 24N 25P 25N 26P 26N 27P 27N 28P 28N 29P 29N 30P 30N LVDCCLK0 LVDSCLK0 LVDSCLK1 LVDSCLK1 31P Signal Name BK0_IO15 BK0_IO16 BK0_IO17 BK0_IO18 GND (Bank 0) BK0_IO19 BK0_IO20 BK0_IO21 BK0_IO22 BK0_IO23 BK0_IO24 BK0_IO25 BK0_IO26 GND (Bank 0) BK0_IO27 BK0_IO28 BK0_IO29 BK0_IO30 BK0_IO31 BK0_IO32 BK0_IO33 BK0_IO38 BK0_IO35 BK0_IO36 BK0_IO39 BK0_IO34 GND (Bank 0) BK0_IO37 BK0_IO40 GND (Bank 0) BK0_IO41 GCLK0 GCLK1 VCCP0 GNDP0 GCLK2 GCLK3 BK1_IO0 LFX500 Second Function HSI0B_SINN HSI1A_SOUTP HSI1A_SOUTN HSI1A_SINP HSI1A_SINN HSI1B_SOUTP HSI1B_SOUTN HSI1B_SINP HSI1B_SINN PLL_RST0 PLL_RST1 PLL_FBK0 PLL_FBK1 CLK_OUT0 CLK_OUT1 CLK_OUT2 LVDS Pair/ Polarity 7N 8P 8N 9P 9N 10P 10N 11P 11N 12P 12N 13P 13N 14P 14N 15P 15N 16P 16N 19P 17N 18P 19N 17P 18N 20P 20N LVDSCLK0 LVDSCLK0 LVDSCLK1 LVDSCLK1 21P 75 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Continued) LFX1200 900 fpBGA Ball T1 U2 U1 U3 U4 V1 V2 U5 U6 V4 V3 V6 V7 W1 W2 W3 W4 W5 W6 Y6 Y5 Y4 Y3 AA5 AA4 Y2 Y1 AB7 AB6 AA2 AA1 AB5 AB4 AB2 Signal Name BK1_IO1 BK1_IO2 GND (Bank 1) BK1_IO3 BK1_IO4 BK1_IO5 BK1_IO6 BK1_IO7 BK1_IO8 BK1_IO9 BK1_IO10 GND (Bank 1) BK1_IO11 BK1_IO12 BK1_IO13 BK1_IO14 BK1_IO15 BK1_IO16 BK1_IO17 BK1_IO18 GND (Bank 1) BK1_IO19 BK1_IO20 BK1_IO21 BK1_IO22 BK1_IO23 BK1_IO24 BK1_IO25 BK1_IO26 GND (Bank 1) BK1_IO27 BK1_IO28 BK1_IO29 BK1_IO30 BK1_IO31 BK1_IO32 BK1_IO33 BK1_IO34 GND (Bank 1) Second Function CLK_OUT3 SS_CLKOUT0P SS_CLKOUT0N PLL_FBK2 PLL_FBK3 SS_CLKIN0P SS_CLKIN0N PLL_RST2 PLL_RST3 HSI3A_SOUTP HSI3A_SOUTN HSI3A_SINP HSI3A_SINN HSI3B_SOUTP LVDS Pair/ Polarity 31N 32P 32N 33P 33N 34P 34N 35P 35N 36P 36N 37P 37N 38P 38N 39P 39N 40P 40N 41P 41N 42P 42N 43P 43N 44P 44N 45P 45N 46P 46N 47P 47N 48P Signal Name GND (Bank 1) BK1_IO1 BK1_IO2 BK1_IO3 BK1_IO4 BK1_IO5 BK1_IO10 BK1_IO11 BK1_IO12 BK1_IO13 BK1_IO6 GND (Bank 1) BK1_IO7 BK1_IO20 BK1_IO21 BK1_IO8 BK1_IO9 BK1_IO14 GND (Bank 1) BK1_IO15 BK1_IO16 BK1_IO17 NC NC NC NC NC NC BK1_IO18 BK1_IO19 NC NC BK1_IO22 GND (Bank 1) BK1_IO23 NC NC NC LFX500 Second Function CLK_OUT3 SS_CLKOUT0P SS_CLKOUT0N PLL_FBK2 PLL_FBK3 SS_CLKIN0P SS_CLKIN0N PLL_RST2 PLL_RST3 HSI2A_SOUTP HSI2A_SOUTN HSI2A_SINP HSI2A_SINN LVDS Pair/ Polarity 21N 22P 22N 23P 23N 26P 26N 27P 27N 24P 24N 31P 31N 25P 25N 28P 28N 29P 29N 30P 30N 32P 32N - 76 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Continued) LFX1200 900 fpBGA Ball AB1 AC6 AC5 AC2 AC1 AC4 AC3 AD2 AD1 AD3 AD4 AE2 AE1 AD5 AD6 AF2 AF1 AE3 AE4 AG1 AG2 AE5 AF4 AH1 AH2 AF3 AG3 AH4 AJ3 AK3 AG5 AH5 AJ4 AK4 AG6 AH6 AJ5 Signal Name BK1_IO35 BK1_IO36 BK1_IO37 BK1_IO38 BK1_IO39 BK1_IO40 BK1_IO41 BK1_IO42 GND (Bank 1) BK1_IO43 BK1_IO44 BK1_IO45 BK1_IO46 BK1_IO47 BK1_IO48 BK1_IO49 BK1_IO50 GND (Bank 1) BK1_IO51 BK1_IO52 BK1_IO53 BK1_IO54 BK1_IO55 BK1_IO56 BK1_IO57 BK1_IO58 GND (Bank 1) BK1_IO59 BK1_IO60 BK1_IO61 TCK TMS TOE BK2_IO0 BK2_IO1 BK2_IO2 GND (Bank 2) BK2_IO3 BK2_IO4 BK2_IO5 BK2_IO6 Second Function HSI3B_SOUTN HSI3B_SINP HSI3B_SINN HSI4A_SOUTP HSI4A_SOUTN HSI4A_SINP HSI4A_SINN VREF1 HSI4B_SOUTP HSI4B_SOUTN HSI4B_SINP HSI4B_SINN LVDS Pair/ Polarity 48N 49P 49N 50P 50N 51P 51N 52P 52N 53P 53N 54P 54N 55P 55N 56P 56N 57P 57N 58P 58N 59P 59N 60P 60N 61P 61N 62P 62N 63P 63N 64P 64N 65P Signal Name NC NC NC NC NC NC NC NC NC BK1_IO32 BK1_IO33 BK1_IO34 BK1_IO35 BK1_IO25 BK1_IO24 BK1_IO26 BK1_IO27 BK1_IO28 BK1_IO29 BK1_IO30 GND (Bank 1) BK1_IO31 BK1_IO36 BK1_IO37 BK1_IO38 GND (Bank 1) BK1_IO39 BK1_IO40 BK1_IO41 TCK TMS TOE BK2_IO0 BK2_IO1 BK2_IO2 GND (Bank 2) BK2_IO3 BK2_IO4 BK2_IO5 BK2_IO6 LFX500 Second Function VREF1 HSI2B_SOUTP HSI2B_SOUTN HSI2B_SINP HSI2B_SINN LVDS Pair/ Polarity 37P 37N 38P 38N 33N 33P 34P 34N 35P 35N 36P 36N 39P 39N 40P 40N 41P 41N 42P 42N 43P 43N 44P 44N 45P 77 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Continued) LFX1200 900 fpBGA Ball AK5 AE7 AF7 AG7 AH7 AE8 AF8 AJ6 AK6 AG8 AH8 AJ7 AK7 AF9 AG9 AJ8 AK8 AD10 AE10 AJ9 AK9 AF10 AG10 AK10 AJ10 AE11 AF11 AG11 AH11 AE12 AF12 AJ11 AK11 AG12 AH12 AK12 Signal Name BK2_IO7 BK2_IO8 BK2_IO9 BK2_IO10 GND (Bank 2) BK2_IO11 BK2_IO12 BK2_IO13 BK2_IO14 BK2_IO15 BK2_IO16 BK2_IO17 BK2_IO18 GND (Bank 2) BK2_IO19 BK2_IO20 BK2_IO21 BK2_IO22 BK2_IO23 BK2_IO24 BK2_IO25 BK2_IO26 GND (Bank 2) BK2_IO27 BK2_IO28 BK2_IO29 BK2_IO30 BK2_IO31 BK2_IO32 BK2_IO33 BK2_IO34 GND (Bank 2) BK2_IO35 BK2_IO36 BK2_IO37 BK2_IO38 BK2_IO39 BK2_IO40 BK2_IO41 BK2_IO42 GND (Bank 2) Second Function VREF2 LVDS Pair/ Polarity 65N 66P 66N 67P 67N 68P 68N 69P 69N 70P 70N 71P 71N 72P 72N 73P 73N 74P 74N 75P 75N 76P 76N 77P 77N 78P 78N 79P 79N 80P 80N 81P 81N 82P 82N 83P Signal Name BK2_IO7 BK2_IO8 BK2_IO9 BK2_IO10 GND (Bank 2) BK2_IO11 BK2_IO21 BK2_IO20 BK2_IO12 BK2_IO13 BK2_IO14 BK2_IO15 BK2_IO16 BK2_IO17 BK2_IO18 GND (Bank 2) BK2_IO19 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC BK2_IO22 LFX500 Second Function VREF2 LVDS Pair/ Polarity 45N 46P 46N 47P 47N 52N 52P 48P 48N 49P 49N 50P 50N 51P 51N 53P - 78 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Continued) LFX1200 900 fpBGA Ball AJ12 AD13 AE13 AK13 AJ13 AG13 AH13 AE14 AF14 AG14 AH14 AJ14 AK14 AE15 AF15 AG15 AH15 AJ15 AK15 AK16 AJ16 AH16 AG16 AF16 AE16 AK17 AJ17 AH17 AG17 AF17 AE17 AH18 AG18 Signal Name BK2_IO43 BK2_IO44 BK2_IO45 BK2_IO46 BK2_IO47 BK2_IO48 BK2_IO49 BK2_IO50 GND (Bank 2) BK2_IO51 BK2_IO52 BK2_IO53 BK2_IO54 BK2_IO55 BK2_IO56 BK2_IO57 BK2_IO58 GND (Bank 2) BK2_IO59 BK2_IO60 BK2_IO61 GND (Bank 2) GND (Bank 3) BK3_IO0 BK3_IO1 BK3_IO2 GND (Bank 3) BK3_IO3 BK3_IO4 BK3_IO5 BK3_IO6 BK3_IO7 BK3_IO8 BK3_IO9 BK3_IO10 GND (Bank 3) BK3_IO11 BK3_IO12 BK3_IO13 Second Function LVDS Pair/ Polarity 83N 84P 84N 85P 85N 86P 86N 87P 87N 88P 88N 89P 89N 90P 90N 91P 91N 92P 92N 93P 93N 94P 94N 95P 95N 96P 96N 97P 97N 98P 98N 99P 99N Signal Name BK2_IO23 BK2_IO24 BK2_IO25 BK2_IO26 GND (Bank 2) BK2_IO27 BK2_IO28 BK2_IO29 BK2_IO30 BK2_IO31 BK2_IO32 BK2_IO33 BK2_IO34 GND (Bank 2) BK2_IO35 BK2_IO36 BK2_IO37 BK2_IO38 BK2_IO39 BK2_IO40 BK2_IO41 GND (Bank 2) GND (Bank 3) BK3_IO0 BK3_IO1 BK3_IO2 BK3_IO3 BK3_IO4 BK3_IO5 BK3_IO6 GND (Bank 3) BK3_IO7 BK3_IO8 BK3_IO9 BK3_IO10 BK3_IO11 BK3_IO12 BK3_IO13 LFX500 Second Function LVDS Pair/ Polarity 53N 54P 54N 55P 55N 56P 56N 57P 57N 58P 58N 59P 59N 60P 60N 61P 61N 62P 62N 63P 63N 64P 64N 65P 65N 66P 66N 67P 67N 68P 68N 69P 69N 79 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Continued) LFX1200 900 fpBGA Ball AJ18 AK18 AE18 AD18 AJ19 AK19 AH19 AG19 AK20 AJ20 AF19 AE19 AH20 AG20 AF20 AE20 AJ21 AK21 AG21 AF21 AK22 AJ22 AE21 AD21 AG22 AF22 AG23 AH23 AJ23 AK23 AF23 AE23 AJ24 AK24 AH24 AG24 Signal Name BK3_IO14 BK3_IO15 BK3_IO16 BK3_IO17 BK3_IO18 GND (Bank 3) BK3_IO19 BK3_IO20 BK3_IO21 BK3_IO22 BK3_IO23 BK3_IO24 BK3_IO25 BK3_IO26 GND (Bank 3) BK3_IO27 BK3_IO28 BK3_IO29 BK3_IO30 BK3_IO31 BK3_IO32 BK3_IO33 BK3_IO34 GND (Bank 3) BK3_IO35 BK3_IO36 BK3_IO37 BK3_IO38 BK3_IO39 BK3_IO40 BK3_IO41 BK3_IO42 GND (Bank 3) BK3_IO43 BK3_IO44 BK3_IO45 BK3_IO46 BK3_IO47 BK3_IO48 BK3_IO49 Second Function VREF3 LVDS Pair/ Polarity 100P 100N 101P 101N 102P 102N 103P 103N 104P 104N 105P 105N 106P 106N 107P 107N 108P 108N 109P 109N 110P 110N 111P 111N 112P 112N 113P 113N 114P 114N 115P 115N 116P 116N 117P 117N Signal Name BK3_IO14 GND (Bank 3) BK3_IO15 BK3_IO16 BK3_IO17 BK3_IO18 BK3_IO19 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC BK3_IO22 GND (Bank 3) BK3_IO23 BK3_IO24 BK3_IO25 BK3_IO26 BK3_IO27 BK3_IO28 BK3_IO29 BK3_IO21 BK3_IO20 LFX500 Second Function VREF3 LVDS Pair/ Polarity 70P 70N 71P 71N 72P 72N 74P 74N 75P 75N 76P 76N 77P 77N 73N 73P 80 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Continued) LFX1200 900 fpBGA Ball AJ25 AK25 AF24 AE24 AK26 AJ26 AH25 AG25 AK27 AJ27 AG26 AH26 AK28 AJ28 AH27 AG28 AF27 AF28 AE26 AE27 AE28 AH30 AH29 AD25 AD26 AG29 AG30 AD27 AD28 AF29 AF30 AC25 AC26 AE29 AE30 AC28 Signal Name BK3_IO50 GND (Bank 3) BK3_IO51 BK3_IO52 BK3_IO53 BK3_IO54 BK3_IO55 BK3_IO56 BK3_IO57 BK3_IO58 GND (Bank 3) BK3_IO59 BK3_IO60 BK3_IO61 RESET DXP DXN BK4_IO0 BK4_IO1 BK4_IO2 GND (Bank 4) BK4_IO3 BK4_IO4 BK4_IO5 BK4_IO6 BK4_IO7 BK4_IO8 BK4_IO9 BK4_IO10 GND (Bank 4) BK4_IO11 BK4_IO12 BK4_IO13 BK4_IO14 BK4_IO15 BK4_IO16 BK4_IO17 BK4_IO18 GND (Bank 4) BK4_IO19 BK4_IO20 Second Function HSI5A_SINP HSI5A_SINN HSI5A_SOUTP HSI5A_SOUTN VREF4 HSI5B_SINP HSI5B_SINN HSI5B_SOUTP HSI5B_SOUTN LVDS Pair/ Polarity 118P 118N 119P 119N 120P 120N 121P 121N 122P 122N 123P 123N 124P 124N 125P 125N 126P 126N 127P 127N 128P 128N 129P 129N 130P 130N 131P 131N 132P 132N 133P 133N 134P Signal Name BK3_IO30 GND (Bank 3) BK3_IO31 BK3_IO32 BK3_IO33 BK3_IO34 BK3_IO35 BK3_IO36 BK3_IO37 BK3_IO38 GND (Bank 3) BK3_IO39 BK3_IO40 BK3_IO41 RESET DXP DXN BK4_IO0 BK4_IO1 BK4_IO2 GND (Bank 4) BK4_IO3 BK4_IO4 BK4_IO5 BK4_IO10 GND (Bank 4) BK4_IO11 BK4_IO12 BK4_IO13 BK4_IO14 BK4_IO15 BK4_IO17 BK4_IO16 BK4_IO6 BK4_IO7 BK4_IO8 BK4_IO9 NC NC NC LFX500 Second Function HSI3A_SINP HSI3A_SINN HSI3A_SOUTP HSI3A_SOUTN VREF4 LVDS Pair/ Polarity 78P 78N 79P 79N 80P 80N 81P 81N 82P 82N 83P 83N 84P 84N 85P 85N 86P 86N 89P 89N 90P 90N 91P 91N 92N 92P 87P 87N 88P 88N - 81 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Continued) LFX1200 900 fpBGA Ball AC27 AD29 AD30 AB24 AB25 AC29 AC30 AB27 AB26 AB30 AB29 AA26 AA27 AA30 AA29 Y25 Y26 Y28 Y27 W25 W26 W27 W28 V24 V25 Y29 Y30 V27 V28 W29 W30 U25 U26 V29 V30 U28 Signal Name BK4_IO21 BK4_IO22 BK4_IO23 BK4_IO24 BK4_IO25 BK4_IO26 GND (Bank 4) BK4_IO27 BK4_IO28 BK4_IO29 BK4_IO30 BK4_IO31 BK4_IO32 BK4_IO33 BK4_IO34 GND (Bank 4) BK4_IO35 BK4_IO36 BK4_IO37 BK4_IO38 BK4_IO39 BK4_IO40 BK4_IO41 BK4_IO42 GND (Bank 4) BK4_IO43 BK4_IO44 BK4_IO45 BK4_IO46 BK4_IO47 BK4_IO48 BK4_IO49 BK4_IO50 GND (Bank 4) BK4_IO51 BK4_IO52 BK4_IO53 BK4_IO54 BK4_IO55 BK4_IO56 Second Function HSI6A_SINP HSI6A_SINN HSI6A_SOUTP HSI6A_SOUTN HSI6B_SINP HSI6B_SINN HSI6B_SOUTP HSI6B_SOUTN PLL_RST4 PLL_RST5 SS_CLKIN1P SS_CLKIN1N PLL_FBK4 LVDS Pair/ Polarity 134N 135P 135N 136P 136N 137P 137N 138P 138N 139P 139N 140P 140N 141P 141N 142P 142N 143P 143N 144P 144N 145P 145N 146P 146N 147P 147N 148P 148N 149P 149N 150P 150N 151P 151N 152P Signal Name NC NC NC NC NC NC NC NC NC BK4_IO18 GND (Bank 4) BK4_IO19 NC NC BK4_IO22 BK4_IO23 NC NC NC NC NC NC BK4_IO24 BK4_IO25 BK4_IO26 GND (Bank 4) BK4_IO27 BK4_IO32 BK4_IO33 BK4_IO20 BK4_IO21 BK4_IO34 GND (Bank 4) BK4_IO35 BK4_IO28 BK4_IO29 BK4_IO30 BK4_IO31 BK4_IO36 LFX500 Second Function HSI3B_SINP HSI3B_SINN HSI3B_SOUTP HSI3B_SOUTN PLL_RST4 PLL_RST5 SS_CLKIN1P SS_CLKIN1N PLL_FBK4 LVDS Pair/ Polarity 93P 93N 95P 95N 96P 96N 97P 97N 100P 100N 94P 94N 101P 101N 98P 98N 99P 99N 102P 82 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Continued) LFX1200 900 fpBGA Ball U27 U29 U30 T30 T29 T28 T27 T26 R28 R27 R26 R29 R30 P30 P29 P27 P28 P26 P25 N27 N28 N29 N30 N25 N24 M29 M30 M28 M27 L30 L29 M26 M25 Signal Name BK4_IO57 BK4_IO58 GND (Bank 4) BK4_IO59 BK4_IO60 BK4_IO61 GND (Bank 4) GCLK4 GCLK5 VCCP1 GNDP1 GCLK6 GCLK7 GND (Bank 5) BK5_IO0 BK5_IO1 BK5_IO2 GND (Bank 5) BK5_IO3 BK5_IO4 BK5_IO5 BK5_IO6 BK5_IO7 BK5_IO8 BK5_IO9 BK5_IO10 GND (Bank 5) BK5_IO11 BK5_IO12 BK5_IO13 BK5_IO14 BK5_IO15 BK5_IO16 BK5_IO17 BK5_IO18 GND (Bank 5) BK5_IO19 BK5_IO20 BK5_IO21 Second Function PLL_FBK5 SS_CLKOUT1P -SS_CLKOUT1N CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 PLL_FBK6 PLL_FBK7 PLL_RST6 PLL_RST7 HSI7A_SINP HSI7A_SINN HSI7A_SOUTP HSI7A_SOUTN HSI7B_SINP HSI7B_SINN LVDS Pair/ Polarity 152N 153P 153N 154P 154N LVDSCLK2 LVDSCLK2 LVDSCLK3 LVDSCLK3 155P 155N 156P 156N 157P 157N 158P 158N 159P 159N 160P 160N 161P 161N 162P 162N 163P 163N 164P 164N 165P 165N Signal Name BK4_IO37 BK4_IO38 BK4_IO39 BK4_IO40 GND (Bank 4) BK4_IO41 GCLK4 GCLK5 VCCP1 GNDP1 GCLK6 GCLK7 BK5_IO0 GND (Bank 5) BK5_IO1 BK5_IO4 GND (Bank 5) BK5_IO7 BK5_IO2 BK5_IO5 BK5_IO6 BK5_IO3 BK5_IO8 BK5_IO9 BK5_IO10 BK5_IO11 BK5_IO12 BK5_IO13 BK5_IO14 GND (Bank 5) BK5_IO15 BK5_IO16 BK5_IO17 BK5_IO18 BK5_IO19 BK5_IO20 BK5_IO21 LFX500 Second Function PLL_FBK5 SS_CLKOUT1P SS_CLKOUT1N CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 PLL_FBK6 PLL_FBK7 PLL_RST6 PLL_RST7 HSI4A_SINP HSI4A_SINN HSI4A_SOUTP HSI4A_SOUTN HSI4B_SINP HSI4B_SINN LVDS Pair/ Polarity 102N 103P 103N 104P 104N LVDSCLK2 LVDSCLK2 LVDSCLK3 LVDSCLK3 105P 105N 107P 108N 106P 107N 108P 106N 109P 109N 110P 110N 111P 111N 112P 112N 113P 113N 114P 114N 115P 115N 83 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Continued) LFX1200 900 fpBGA Ball K30 K29 L28 L27 L26 L25 K27 K26 J30 J29 J26 J27 H30 H29 J25 J24 G30 G29 H27 H28 F30 F29 G27 G28 E30 E29 H26 H25 D30 D29 F28 F27 C30 C29 G26 Signal Name BK5_IO22 BK5_IO23 BK5_IO24 BK5_IO25 BK5_IO26 GND (Bank 5) BK5_IO27 BK5_IO28 BK5_IO29 BK5_IO30 BK5_IO31 BK5_IO32 BK5_IO33 BK5_IO34 GND (Bank 5) BK5_IO35 BK5_IO36 BK5_IO37 BK5_IO38 BK5_IO39 BK5_IO40 BK5_IO41 BK5_IO42 GND (Bank 5) BK5_IO43 BK5_IO44 BK5_IO45 BK5_IO46 BK5_IO47 BK5_IO48 BK5_IO49 BK5_IO50 GND (Bank 5) BK5_IO51 BK5_IO52 BK5_IO53 BK5_IO54 BK5_IO55 BK5_IO56 Second Function HSI7B_SOUTP HSI7B_SOUTN HSI8A_SINP HSI8A_SINN HSI8A_SOUTP HSI8A_SOUTN HSI8B_SINP HSI8B_SINN HSI8B_SOUTP HSI8B_SOUTN HSI9A_SINP HSI9A_SINN HSI9A_SOUTP HSI9A_SOUTN VREF5 HSI9B_SINP HSI9B_SINN HSI9B_SOUTP HSI9B_SOUTN LVDS Pair/ Polarity 166P 166N 167P 167N 168P 168N 169P 169N 170P 170N 171P 171N 172P 172N 173P 173N 174P 174N 175P 175N 176P 176N 177P 177N 178P 178N 179P 179N 180P 180N 181P 181N 182P 182N 183P Signal Name BK5_IO22 GND (Bank 5) BK5_IO23 BK5_IO24 BK5_IO25 BK5_IO26 BK5_IO27 BK5_IO28 BK5_IO29 BK5_IO30 GND (Bank 5) BK5_IO31 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC BK5_IO33 BK5_IO32 BK5_IO34 BK5_IO35 BK5_IO36 BK5_IO37 BK5_IO38 GND (Bank 5) BK5_IO39 NC LFX500 Second Function HSI4B_SOUTP HSI4B_SOUTN HSI5A_SINP HSI5A_SINN HSI5A_SOUTP HSI5A_SOUTN VREF5 HSI5B_SINP HSI5B_SINN HSI5B_SOUTP HSI5B_SOUTN LVDS Pair/ Polarity 116P 116N 117P 117N 118P 118N 119P 119N 120P 120N 121N 121P 122P 122N 123P 123N 124P 124N - 84 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Continued) LFX1200 900 fpBGA Ball G25 F26 E28 E27 D28 C27 B28 A28 D26 C26 B27 A27 D25 C25 B26 A26 F24 E24 A25 B25 D24 C24 A24 B24 F23 E23 A23 B23 C23 D23 E22 D22 G21 F21 B22 A22 E21 Signal Name BK5_IO57 BK5_IO58 GND (Bank 5) BK5_IO59 BK5_IO60 BK5_IO61 CFG0 DONE PROGRAMb BK6_IO0 BK6_IO1 BK6_IO2 GND (Bank 6) BK6_IO3 BK6_IO4 BK6_IO5 BK6_IO6 BK6_IO7 BK6_IO8 BK6_IO9 BK6_IO10 GND (Bank 6) BK6_IO11 BK6_IO12 BK6_IO13 BK6_IO14 BK6_IO15 BK6_IO16 BK6_IO17 BK6_IO18 GND (Bank 6) BK6_IO19 BK6_IO20 BK6_IO21 BK6_IO22 BK6_IO23 BK6_IO24 BK6_IO25 BK6_IO26 GND (Bank 6) BK6_IO27 BK6_IO28 Second Function INITb CCLK CSb Read VREF6 LVDS Pair/ Polarity 183N 184P 184N 185P 185N 186P 186N 187P 187N 188P 188N 189P 189N 190P 190N 191P 191N 192P 192N 193P 193N 194P 194N 195P 195N 196P 196N 197P 197N 198P 198N 199P 199N 200P Signal Name NC NC NC BK5_IO40 BK5_IO41 CFG0 DONE PROGRAMb BK6_IO0 BK6_IO1 BK6_IO2 GND (Bank 6) BK6_IO3 BK6_IO4 BK6_IO5 BK6_IO6 BK6_IO7 BK6_IO8 BK6_IO9 BK6_IO10 GND (Bank 6) BK6_IO11 BK6_IO21 BK6_IO20 BK6_IO12 BK6_IO13 BK6_IO14 BK6_IO15 BK6_IO16 BK6_IO17 NC NC NC NC NC NC NC NC NC LFX500 Second Function INITb CCLK CSb READ VREF6 LVDS Pair/ Polarity 125P 125N 126P 126N 127P 127N 128P 128N 129P 129N 130P 130N 131P 131N 136N 136P 132P 132N 133P 133N 134P 134N - 85 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Continued) LFX1200 900 fpBGA Ball D21 A21 B21 F20 E20 D20 C20 F19 E19 B20 A20 D19 C19 A19 B19 G18 F18 A18 B18 D18 C18 F17 E17 D17 C17 B17 A17 F16 E16 D16 C16 B16 A16 A15 Signal Name BK6_IO29 BK6_IO30 BK6_IO31 BK6_IO32 BK6_IO33 BK6_IO34 GND (Bank 6) BK6_IO35 BK6_IO36 BK6_IO37 BK6_IO38 BK6_IO39 BK6_IO40 BK6_IO41 BK6_IO42 GND (Bank 6) BK6_IO43 BK6_IO44 BK6_IO45 BK6_IO46 BK6_IO47 BK6_IO48 BK6_IO49 BK6_IO50 GND (Bank 6) BK6_IO51 BK6_IO52 BK6_IO53 BK6_IO54 BK6_IO55 BK6_IO56 BK6_IO57 BK6_IO58 GND (Bank 6) BK6_IO59 BK6_IO60 BK6_IO61 GND (Bank 6) GND (Bank 7) BK7_IO0 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Second Function DATA7 DATA6 LVDS Pair/ Polarity 200N 201P 201N 202P 202N 203P 203N 204P 204N 205P 205N 206P 206N 207P 207N 208P 208N 209P 209N 210P 210N 211P 211N 212P 212N 213P 213N 214P 214N 215P 215N 216P 216N 217P Signal Name NC NC NC BK6_IO18 GND (Bank 6) BK6_IO19 NC NC BK6_IO22 BK6_IO23 NC NC NC NC NC NC BK6_IO24 BK6_IO25 BK6_IO32 BK6_IO33 BK6_IO34 GND (Bank 6) BK6_IO35 BK6_IO26 GND (Bank 6) BK6_IO27 BK6_IO28 BK6_IO29 BK6_IO30 BK6_IO31 BK6_IO36 BK6_IO37 BK6_IO38 BK6_IO39 BK6_IO40 BK6_IO41 GND (Bank 6) GND (Bank 7) BK7_IO0 LFX500 Second Function DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 LVDS Pair/ Polarity 135P 135N 137P 137N 138P 138N 142P 142N 143P 143N 139P 139N 140P 140N 141P 141N 144P 144N 145P 145N 146P 146N 147P 86 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Continued) LFX1200 900 fpBGA Ball B15 C15 D15 E15 F15 A14 B14 C14 D14 E14 F14 C13 D13 B13 A13 F13 G13 A12 B12 C12 D12 A11 B11 E12 F12 C11 D11 E11 F11 B10 A10 D10 E10 A9 B9 Signal Name BK7_IO1 BK7_IO2 GND (Bank 7) BK7_IO3 BK7_IO4 BK7_IO5 BK7_IO6 BK7_IO7 BK7_IO8 BK7_IO9 BK7_IO10 GND (Bank 7) BK7_IO11 BK7_IO12 BK7_IO13 BK7_IO14 BK7_IO15 BK7_IO16 BK7_IO17 BK7_IO18 GND (Bank 7) BK7_IO19 BK7_IO20 BK7_IO21 BK7_IO22 BK7_IO23 BK7_IO24 BK7_IO25 BK7_IO26 GND (Bank 7) BK7_IO27 BK7_IO28 BK7_IO29 BK7_IO30 BK7_IO31 BK7_IO32 BK7_IO33 BK7_IO34 GND (Bank 7) BK7_IO35 Second Function LVDS Pair/ Polarity 217N 218P 218N 219P 219N 220P 220N 221P 221N 222P 222N 223P 223N 224P 224N 225P 225N 226P 226N 227P 227N 228P 228N 229P 229N 230P 230N 231P 231N 232P 232N 233P 233N 234P 234N BK7_IO3 BK7_IO4 BK7_IO5 BK7_IO6 GND (Bank 7) BK7_IO7 BK7_IO8 BK7_IO9 BK7_IO10 BK7_IO11 BK7_IO12 BK7_IO13 BK7_IO14 GND (Bank 7) BK7_IO15 BK7_IO16 BK7_IO17 BK7_IO18 BK7_IO19 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Signal Name BK7_IO1 BK7_IO2 LFX500 Second Function LVDS Pair/ Polarity 147N 148P 148N 149P 149N 150P 150N 151P 151N 152P 152N 153P 153N 154P 154N 155P 155N 156P 156N - 87 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Continued) LFX1200 900 fpBGA Ball F10 G10 A8 B8 D9 E9 A7 B7 C8 D8 A6 B6 E8 F8 C7 D7 E7 F7 A5 B5 C6 D6 D5 C5 B4 A4 A3 B3 C4 Signal Name BK7_IO36 BK7_IO37 BK7_IO38 BK7_IO39 BK7_IO40 BK7_IO41 BK7_IO42 GND (Bank 7) BK7_IO43 BK7_IO44 BK7_IO45 BK7_IO46 BK7_IO47 BK7_IO48 BK7_IO49 BK7_IO50 GND (Bank 7) BK7_IO51 BK7_IO52 BK7_IO53 BK7_IO54 BK7_IO55 BK7_IO56 BK7_IO57 BK7_IO58 GND (Bank 7) BK7_IO59 BK7_IO60 BK7_IO61 TDO VCCJ TDI Second Function VREF7 LVDS Pair/ Polarity 235P 235N 236P 236N 237P 237N 238P 238N 239P 239N 240P 240N 241P 241N 242P 242N 243P 243N 244P 244N 245P 245N 246P 246N 247P 247N BK7_IO25 BK7_IO26 BK7_IO27 BK7_IO21 BK7_IO20 BK7_IO28 BK7_IO29 BK7_IO30 GND (Bank 7) BK7_IO31 BK7_IO32 BK7_IO33 BK7_IO34 BK7_IO35 BK7_IO36 BK7_IO37 BK7_IO38 GND (Bank 7) BK7_IO39 BK7_IO40 BK7_IO41 TDO VCCJ TDI Signal Name NC NC NC NC BK7_IO22 GND (Bank 7) BK7_IO23 BK7_IO24 LFX500 Second Function VREF7 LVDS Pair/ Polarity 158P 158N 159P 159N 160P 160N 157N 157P 161P 161N 162P 162N 163P 163N 164P 164N 165P 165N 166P 166N 167P 167N - 88 Lattice Semiconductor ispXPGA Family Data Sheet Part Number Description LFX XXXX X - XX XXXXX X Device Family LFX Gates 125 = 125K Gates 200 = 200K Gates 500 = 500K Gates 1200 = 1200K Gates Power Supply Voltage B = 2.5/3.3V C = 1.8V Grade C = Commercial I = Industrial Package F900 = 900-Ball fpBGA Speed 4 = Fastest 3 = Slowest Ordering Information Commercial1 Part Number LFX1200B-04F900C LFX1200B-03F900C LFX1200C-04F900C LFX1200C-03F900C Gates 1200K 1200K 1200K 1200K Voltage 2.5/3.3 2.5/3.3 1.8 1.8 Speed Grade -4 -3 -4 -3 Package fpBGA fpBGA fpBGA fpBGA Balls 900 900 900 900 Industrial1 Part Number LFX1200B-03F900I LFX1200C-03F900I Gates 1200K 1200K Voltage 2.5/3.3 1.8 Speed Grade -3 -3 Package fpBGA fpBGA Balls 900 900 1. The ispXPGA family is dual-marked with both Commercial and Industrial grades. The Commercial speed grade is one speed grade faster (i.e. LFX1200B-04FE900C) than the Industrial speed grade (i.e. LFX1200B-03FE900I). For Further Information In addition to this data sheet, the following Lattice technical notes may be helpful when designing with the ispXPGA Family: * * * * * ispXPGA sysMEM Memory Design and Usage Guidelines (TN1028) Lattice sysCLOCK PLL Design and Usage Guidelines (TN1003) sysIO Usage Guidelines for Lattice Devices (TN1000) ispXP Configuration Usage Guidelines (TN1026) sysHSI Usage Guide (TN1020) 89 |
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